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PCI1420 pc card controllers data manual literature number: scps047 april 1999 printed on recycled paper
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated
iii contents section title page 1 introduction 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 description 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 features 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 related documents 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 ordering information 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 terminal descriptions 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 feature/protocol descriptions 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 power supply sequencing 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 i/o characteristics 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 clamping voltages 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 peripheral component interconnect (pci) interface 32 . . . . . . . . . . . . . . 3.4.1 pci bus lock (lock ) 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 loading subsystem identification 33 . . . . . . . . . . . . . . . . . . . . . 3.5 pc card applications 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 pc card insertion/removal and recognition 33 . . . . . . . . . . . 3.5.2 p 2 c power-switch interface (tps2206/2216) 34 . . . . . . . . . . 3.5.3 zoomed video support 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 ultra zoomed video 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 internal ring oscillator 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.6 integrated pullup resistors 37 . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.7 spkrout and caudpwm usage 37 . . . . . . . . . . . . . . . . . . . 3.5.8 led socket activity indicators 38 . . . . . . . . . . . . . . . . . . . . . . . . 3.5.9 pc card-16 distributed dma support 38 . . . . . . . . . . . . . . . . . 3.5.10 pc card-16 pc/pci dma 310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.11 cardbus socket registers 310 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 serial bus interface 311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 serial bus interface implementation 311 . . . . . . . . . . . . . . . . . . . 3.6.2 serial bus interface protocol 311 . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 serial bus eeprom application 313 . . . . . . . . . . . . . . . . . . . . . . 3.6.4 serial bus power switch application 314 . . . . . . . . . . . . . . . . . . 3.6.5 accessing serial bus devices through software 315 . . . . . . . . 3.7 programmable interrupt subsystem 315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 pc card functional and card status change interrupts 315 . 3.7.2 interrupt masks and flags 317 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 using parallel irq interrupts 318 . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 using parallel pci interrupts 318 . . . . . . . . . . . . . . . . . . . . . . . . .
iv 3.7.5 using serialized irqser interrupts 319 . . . . . . . . . . . . . . . . . . . 3.7.6 smi support in the PCI1420 319 . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 power management overview 319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 clock run protocol 320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 cardbus pc card power management 320 . . . . . . . . . . . . . . . . 3.8.3 16-bit pc card power management 320 . . . . . . . . . . . . . . . . . . . 3.8.4 suspend mode 320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.5 requirements for suspend mode 321 . . . . . . . . . . . . . . . . . . . . . 3.8.6 ring indicate 322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.7 pci power management 322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.8 cardbus device class power management 323 . . . . . . . . . . . . 3.8.9 acpi support 324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.10 master list of pme context bits and global reset only bits 324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pc card controller programming model 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 pci configuration registers (functions 0 and 1) 41 . . . . . . . . . . . . . . . . . 4.2 vendor id register 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 device id register 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 command register 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 status register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 revision id register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 pci class code register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 cache line size register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 latency timer register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 header type register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 bist register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 cardbus socket registers/exca base-address register 47 . . . . . . . . . 4.13 capability pointer register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 secondary status register 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 pci bus number register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 cardbus bus number register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 subordinate bus number register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 cardbus latency timer register 410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 memory base registers 0, 1 410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 memory limit registers 0, 1 411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.21 i/o base registers 0, 1 411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 i/o limit registers 0, 1 412 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 interrupt line register 412 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24 interrupt pin register 413 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.25 bridge control register 414 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.26 subsystem vendor id register 415 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.27 subsystem id register 415 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 pc card 16-bit i/f legacy-mode base address register 415 . . . . . . . . . 4.29 system control register 416 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v 4.30 multifunction routing register 419 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 retry status register 421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.32 card control register 422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.33 device control register 423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.34 diagnostic register 424 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.35 socket dma register 0 425 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.36 socket dma register 1 426 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.37 capability id register 427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.38 next-item pointer register 427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.39 power management capabilities register 428 . . . . . . . . . . . . . . . . . . . . . . 4.40 power management control/status register 429 . . . . . . . . . . . . . . . . . . . . 4.41 power management control/status register bridge support extensions 430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.42 power management data register 430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.43 general-purpose event status register 431 . . . . . . . . . . . . . . . . . . . . . . . . 4.44 general-purpose event enable register 432 . . . . . . . . . . . . . . . . . . . . . . . 4.45 general-purpose input register 433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.46 general-purpose output register 434 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.47 serial bus data register 434 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.48 serial bus index register 435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.49 serial bus slave address register 435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.50 serial bus control and status register 436 . . . . . . . . . . . . . . . . . . . . . . . . . 5 exca compatibility registers (functions 0 and 1) 51 . . . . . . . . . . . . . . . . . . 5.1 exca identification and revision register (index 00h) 55 . . . . . . . . . . . 5.2 exca interface status register (index 01h) 56 . . . . . . . . . . . . . . . . . . . . . 5.3 exca power control register (index 02h) 57 . . . . . . . . . . . . . . . . . . . . . . 5.4 exca interrupt and general-control register (index 03h) 58 . . . . . . . . . 5.5 exca card status-change register (index 04h) 59 . . . . . . . . . . . . . . . . . 5.6 exca card status-change-interrupt configuration register (index 05h) 510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 exca address window enable register (index 06h) 511 . . . . . . . . . . . . . 5.8 exca i/o window control register (index 07h) 512 . . . . . . . . . . . . . . . . . 5.9 exca i/o windows 0 and 1 start-address low-byte registers (index 08h, 0ch) 513 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 exca i/o windows 0 and 1 start-address high-byte registers (index 09h, 0dh) 513 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 exca i/o windows 0 and 1 end-address low-byte registers (index 0ah, 0eh) 514 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 exca i/o windows 0 and 1 end-address high-byte registers (index 0bh, 0fh) 514 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 exca memory windows 04 start-address low-byte registers (index 10h, 18h, 20h, 28h, 30h) 515 . . . . . . . . . . . . . . . . . . . . . . 5.14 exca memory windows 04 start-address high-byte registers (index 11h, 19h, 21h, 29h, 31h) 516 . . . . . . . . . . . . . . . . . . . . . . 5.15 exca memory windows 04 end-address low-byte registers (index 12h, 1ah, 22h, 2ah, 32h) 517 . . . . . . . . . . . . . . . . . . . . . .
vi 5.16 exca memory windows 04 end-address high-byte registers (index 13h, 1bh, 23h, 2bh, 33h) 518 . . . . . . . . . . . . . . . . . . . . . 5.17 exca memory windows 04 offset-address low-byte registers (index 14h, 1ch, 24h, 2ch, 34h) 519 . . . . . . . . . . . . . . . . . . . . . 5.18 exca memory windows 04 offset-address high-byte registers (index 15h, 1dh, 25h, 2dh, 35h) 520 . . . . . . . . . . . . . . . . . . . . . 5.19 exca i/o windows 0 and 1 offset-address low-byte registers (index 36h, 38h) 521 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.20 exca i/o windows 0 and 1 offset-address high-byte registers (index 37h, 39h) 521 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.21 exca card detect and general control register (index 16h) 522 . . . . . . 5.22 exca global control register (index 1eh) 523 . . . . . . . . . . . . . . . . . . . . . . 5.23 exca memory windows 04 page register 524 . . . . . . . . . . . . . . . . . . . . 6 cardbus socket registers (functions 0 and 1) 61 . . . . . . . . . . . . . . . . . . . . . . 6.1 socket event register 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 socket mask register 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 socket present state register 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 socket force event register 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 socket control register 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 socket power management register 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 distributed dma (ddma) registers 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 dma current address/base address register 71 . . . . . . . . . . . . . . . . . . . 7.2 dma page register 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 dma current count/base count register 72 . . . . . . . . . . . . . . . . . . . . . . . 7.4 dma command register 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 dma status register 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 dma request register 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 dma mode register 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 dma master clear register 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 dma multichannel/mask register 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electrical characteristics 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 absolute maximum ratings over operating temperature ranges 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 recommended operating conditions 82 . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 electrical characteristics over recommended operating conditions 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 pci clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature 83 . . . 8.5 pci timing requirements over recommended ranges of supply voltage and operating free-air temperature 84 . . . . . . . . . . . 9 mechanical information 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii list of illustrations figure title page 21 pci-to-cardbus pin diagram 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 pci-to-pc card (16-bit) diagram 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PCI1420 simplified block diagram 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3-state bidirectional buffer 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 tps2206 terminal assignments 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 tps2206 typical application 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 zoomed video implementation using PCI1420 35 . . . . . . . . . . . . . . . . . . . . . . . 36 zoomed video switching application 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 sample application of spkrout and caudpwm 38 . . . . . . . . . . . . . . . . . . . . 38 two sample led circuits 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 serial eeprom application 311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 serial bus start/stop conditions and bit transfers 312 . . . . . . . . . . . . . . . . . . . 311 serial bus protocol acknowledge 312 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 serial bus protocol byte write 313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 serial bus protocol byte read 313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 eeprom interface doubleword data collection 313 . . . . . . . . . . . . . . . . . . . . . 315 eeprom data format 314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 send byte protocol 315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 irq implementation 318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 suspend functional implementation 321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 signal diagram of suspend function 321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 ri_out functional diagram 322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 block diagram of a status/enable cell 324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 exca register access through i/o 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 exca register access through memory 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 accessing cardbus socket registers through pci memory 61 . . . . . . . . . . . .
viii list of tables table title page 21 cardbus pc card signal names by ghk/pdv pin number 23 . . . . . . . . . . . . 22 cardbus pc card signal names sorted alphabetically 24 . . . . . . . . . . . . . . . . 23 16-bit pc card signal names by ghk/pdv pin number 25 . . . . . . . . . . . . . . . 24 16-bit pc card signal names sorted alphabetically 27 . . . . . . . . . . . . . . . . . . . 25 power supply 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 pc card power switch 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 pci system 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 pci address and data 210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 pci interface control 211 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 multifunction and miscellaneous pins 212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16-bit pc card address and data (slots a and b) 213 . . . . . . . . . . . . . . . . . . . . 212 16-bit pc card interface control (slots a and b) 214 . . . . . . . . . . . . . . . . . . . . . 213 cardbus pc card interface system (slots a and b) 216 . . . . . . . . . . . . . . . . . . 214 cardbus pc card address and data (slots a and b) 217 . . . . . . . . . . . . . . . . . 215 cardbus pc card interface control (slots a and b) 218 . . . . . . . . . . . . . . . . . . 31 pc card card-detect and voltage-sense connections 34 . . . . . . . . . . . . . . . . 32 pc card card-detect and voltage-sense connections 36 . . . . . . . . . . . . . . . . 33 distributed dma registers 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 pc/pci channel assignments 310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 i/o addresses used for pc/pci dma 310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 cardbus socket registers 311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 registers and bits loadable through serial eeprom 313 . . . . . . . . . . . . . . . . . 38 PCI1420 registers used to program serial bus devices 315 . . . . . . . . . . . . . . . 39 interrupt mask and flag registers 316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 pc card interrupt events and description 317 . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 interrupt pin register cross reference 319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 smi control 319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 power management registers 323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 pci configuration registers (functions 0 and 1) 41 . . . . . . . . . . . . . . . . . . . . . . 42 command register 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 status register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 secondary status register 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 interrupt pin register cross reference 413 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 bridge control register 414 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 system control register 417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 multifunction routing register 419 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 retry status register 421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix 410 card control register 422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 device control register 423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 diagnostic register 424 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 socket dma register 0 425 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 socket dma register 1 426 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 power management capabilities register 428 . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 power management control/status register 429 . . . . . . . . . . . . . . . . . . . . . . . . 417 power management control/status register bridge support extensions 430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 general-purpose event status register 431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 general-purpose event enable register 432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 general-purpose input register 433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 general-purpose output register 434 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 serial bus data register 434 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 serial bus index register 435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 serial bus slave address register 435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 serial bus control and status register 436 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 exca registers and offsets 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 exca identification and revision register (index 00h) 55 . . . . . . . . . . . . . . . . . 53 exca interface status register (index 01h) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . 54 exca power control register 82365sl support (index 02h) 57 . . . . . . . . . . . 55 exca power control register 82365sl-df support (index 02h) 57 . . . . . . . . 56 exca interrupt and general-control register (index 03h) 58 . . . . . . . . . . . . . . 57 exca card status-change register (index 04h) 59 . . . . . . . . . . . . . . . . . . . . . . 58 exca card status-change-interrupt configuration register (index 05h) 510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 exca address window enable register (index 06h) 511 . . . . . . . . . . . . . . . . . . 510 exca i/o window control register (index 07h) 512 . . . . . . . . . . . . . . . . . . . . . . 511 exca memory windows 04 start-address high-byte registers (index 11h, 19h, 21h, 29h, 31h) 516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 exca memory windows 04 end-address high-byte registers (index 13h, 1bh, 23h, 2bh, 33h) 518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 exca memory windows 04 offset-address high-byte registers (index 15h, 1dh, 25h, 2dh, 35h) 520 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 exca card detect and general control register (index 16h) 522 . . . . . . . . . . 515 exca global control register (index 1eh) 523 . . . . . . . . . . . . . . . . . . . . . . . . . . 61 cardbus socket registers 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 socket event register 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 socket mask register 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 socket present state register 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 socket force event register 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 socket control register 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 socket power management register 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x 71 distributed dma registers 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 dma command register 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 dma status register 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 dma mode register 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 dma multichannel/mask register 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 1 introduction 1.1 description the ti PCI1420, the industry's first 208-pin controller to meet the pci bus power management interface specification for pci to cardbus bridges , is a high-performance pci-to-cardbus controller that supports two independent card sockets compliant with the 1997 pc card standard . the PCI1420 provides features that make it the best choice for bridging between pci and pc cards in both notebook and desktop computers. the 1997 pc card standard retains the 16-bit pc card specification defined in pci local bus specification and defines the new 32-bit pc card, cardbus, capable of full 32-bit data transfers at 33 mhz. the PCI1420 supports any combination of 16-bit and cardbus pc cards in the two sockets, powered at 5 v or 3.3 v, as required. the PCI1420 is compliant with the pci local bus specification , and its pci interface can act as either a pci master device or a pci slave device. the pci bus mastering is initiated during 16-bit pc card dma transfers or cardbus pc card bridging transactions. the PCI1420 is also compliant with the latest pci bus power management interface specification . all card signals are internally buffered to allow hot insertion and removal without external buffering. the PCI1420 is register compatible with the intel 82365sl-df and 82365sl exca controllers. the PCI1420 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit pci cycles for maximum performance. independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. the PCI1420 can also be programmed to accept fast posted writes to improve system-bus utilization. multiple system-interrupt signaling options are provided, including: parallel pci, parallel isa, serialized isa, and serialized pci. furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. many other features designed into the PCI1420, such as socket activity light-emitting diode (led) outputs, are discussed in detail throughout the design specification. an advanced complementary metal-oxide semiconductor (cmos) process achieves low system power consumption while operating at pci clock rates up to 33 mhz. several low-power modes enable the host power management system to further reduce power consumption. 1.2 features the PCI1420 supports the following features: ? fully compatible with the intel ? 430tx (mobile triton ii) chipset ? a 208-pin low-profile qfp (pdv) or microstar ball grid array (ghk) package ? 3.3-v core logic with universal pci interfaces compatible with 3.3-v and 5-v pci signaling environments ? mix-and-match 5-v/3.3-v 16-bit pc cards and 3.3-v cardbus cards ? two pc card or cardbus slots with hot insertion and removal ? uses serial interface to ti ? tps2206/2216 dual-slot pc card power switch ? burst transfers to maximize data throughput with cardbus cards ? parallel pci interrupts, parallel isa irq and parallel pci interrupts, serial isa irq with parallel pci interrupts, and serial isa irq and pci interrupts ? serial eeprom interface for loading subsystem id and subsystem vendor id ? pipelined architecture allows greater than 130m bps throughput from cardbus-to-pci and from pci-to-cardbus
12 ? up to five general-purpose i/os ? programmable output select for clkrun ? multifunction pci device with separate configuration space for each socket ? five pci memory windows and two i/o windows available for each r2 socket ? two i/o windows and two memory windows available to each cardbus socket ? exchangeable card architecture (exca) compatible registers are mapped in memory and i/o space ? intel 82365sl-df and 82365sl register compatible ? distributed dma (ddma) and pc/pci dma ? 16-bit dma on both pc card sockets ? ring indicate, suspend , pci clkrun, and cardbus cclkrun ? socket activity led pins ? pci bus lock (lock ) ? advanced submicron, low-power cmos technology ? internal ring oscillator 1.3 related documents ? advanced configuration and power interface (acpi) specification (revision 1.0) ? pci bus power management interface specification (revision 1.1) ? pci bus power management interface specification for pci to cardbus bridges (revision 0.6) ? pci to pcmcia cardbus bridge register description (yenta) (revision 2.1) ? pci local bus specification (revision 2.2) ? pci mobile design guide (revision 1.0) ? pci14xx implemenation guide for d3 wake-up ? 1997 pc card ? standard ? pc 99 ? serialized irq support for pci systems (revision 6) 1.4 ordering information ordering number name voltage package PCI1420 pc card controller 3.3 v, 5-v tolerant i/os 208-pin lqfp 209-ball pbga
21 2 terminal descriptions b_cclkrun a_cad25 a_cad13 a_cad0 b_cad9 b_cad1 b_ccd1 ad4 ad17 ccp ad10 ad9 ad8 ad7 ad6 ad5 ad3 gnd ad1 ad0 b_cad0 b_cad2 b_cad4 b_cad3 gnd b_cad6 b_cad5 b_rsvd b_cad7 b_cc/be0 b_cad10 b_cad11 b_cad14 b_cad12 b_cad15 b_cad16 b_cpar b_cperr gnd b_cstop b_cgnt b_cirdy b_cdevsel b_cclk b_ctrdy b_cframe b_cc/be2 ad2 b_cad8 b_cad13 b_cc/be1 b_rsvd b_cblock mfunc2 c/be3 ri_out/pme ad25 gnd req prst ad11 ad31 ad30 ad29 ad28 ad27 ad24 pclk gnd idsel ad22 ad20 ad26 ad23 ad16 frame gnd irdy devsel perr serr par ad15 ad14 ad13 gnd ad12 a_cc/be1 a_cad16 a_cad14 a_cad12 a_cad11 a_cad10 gnd a_cad7 a_cad9 a_cc/be0 a_cad8 a_rsvd a_cad5 a_cad6 a_cad4 a_cad1 a_cad2 a_ccd1 b_cad31 b_rsvd b_cad30 b_cad29 b_cad28 b_cad27 gnd b_ccd2 b_cstschg b_caudio b_cvs1 b_cad26 b_cad25 b_cserr b_cc/be3 b_cad24 v b_cad23 b_creq b_cad22 b_cad21 b_crst b_cad20 b_cvs2 b_cad19 b_cad18 b_cad17 158 157 160 159 162 161 164 163 166 165 168 167 170 169 172 171 174 173 176 175 178 177 180 179 182 181 184 183 186 185 188 187 190 189 192 191 194 193 196 195 198 197 200 199 202 201 204 203 206 205 208 207 103 104 101 102 99 100 97 98 95 96 93 94 91 92 89 90 87 88 85 86 83 84 81 82 79 80 77 78 75 76 73 74 71 72 69 70 67 68 65 66 63 64 61 62 59 60 57 58 55 56 53 54 a_cad3 b_cint a_cad15 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 48 47 50 49 52 51 106 105 108 107 110 109 112 111 114 113 116 115 118 117 120 119 122 121 124 123 126 125 128 127 130 129 132 131 134 133 136 135 138 137 140 139 142 141 144 143 146 145 148 147 150 149 152 151 154 153 156 155 suspend gnd mfunc0 data spkrout latch clock a_cad31 a_cad30 a_rsvd a_cad28 a_cad29 a_ccd2 a_cad27 a_cclkrun a_caudio a_cstschg a_cint a_cserr a_cad26 a_cvs1 a_cc/be3 a_cad24 a_cad23 gnd a_cad21 a_cad22 a_creq a_cad20 a_crst a_cad19 a_cvs2 a_cad18 a_cframe a_cc/be2 a_ctrdy a_cirdy a_cclk v a_cdevsel a_cad17 a_cstop a_cgnt a_cblock a_cperr a_rsvd a_cpar gnt ad21 ad19 ad18 trdy stop v c/be0 cc v cc v ccb v cc v cc cc v cca v cc mfunc1 mfunc3 mfunc4 mfunc5 mfunc6 v cc grst v cc c/be2 v cc c/be1 ccp v card a card b PCI1420 core pci pdv low-profile quad flat package top view v cci figure 21. pci-to-cardbus pin diagram
22 c/be1 b_cd1 a_a1 a_d3 b_a10 b_d4 ad4 ad18 ccp ad10 ad9 ad8 ad7 ad6 ad5 ad3 gnd ad1 ad0 b_d3 b_d11 b_d12 b_d5 gnd b_d13 b_d6 b_d14 b_d7 b_ce1 b_a9 b_a11 b_a17 b_a13 b_a14 gnd b_a20 b_we b_a15 b_a21 b_a16 b_a22 b_a23 b_a12 ad2 b_d15 b_a8 b_a18 b_a19 mfunc2 ad26 c/be3 ad28 gnd prst gnt req ad31 ad30 ad11 ad27 pclk gnd ad24 ad23 ad21 ad29 idsel ad17 frame gnd irdy devsel perr serr par ad15 ad14 ad13 gnd ad12 a_a8 a_a17 a_a9 a_a11 gnd a_d7 a_a10 a_d15 a_d14 a_d6 a_d13 a_d12 a_d4 a_d11 a_cd1 b_d10 b_d2 b_d9 b_d1 b_d8 b_d0 gnd b_cd2 b_wp(iois16) b_bvd1(stschg/ri) b_vs1 b_a0 b_a1 b_wait b_reg b_a2 v b_a3 b_inpack b_a4 b_a5 b_reset b_a6 b_a25 b_a7 b_a24 158 157 160 159 162 161 164 163 166 165 168 167 170 169 172 171 174 173 176 175 178 177 180 179 182 181 184 183 186 185 188 187 190 189 192 191 194 193 196 195 198 197 200 199 202 201 204 203 206 205 208 207 103 104 101 102 99 100 97 98 95 96 93 94 91 92 89 90 87 88 85 86 83 84 81 82 79 80 77 78 75 76 73 74 71 72 69 70 67 68 65 66 63 64 61 62 59 60 57 58 55 56 53 54 a_d5 b_ready(ireq) a_iowr 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 48 47 50 49 52 51 106 105 108 107 110 109 112 111 114 113 116 115 118 117 120 119 122 121 124 123 126 125 128 127 130 129 132 131 134 133 136 135 138 137 140 139 142 141 144 143 146 145 148 147 150 149 152 151 154 153 156 155 spkrout gnd mfunc0 data latch clock a_d10 a_d9 a_d2 a_d8 a_d1 a_cd2 a_d0 a_wp(iois16) a_bvd1(stschg/ri) a_ready(ireq) a_wait a_a0 a_vs1 a_reg a_a2 a_a3 gnd a_a5 a_a4 a_inpack a_a6 a_reset a_a25 a_vs2 a_a7 a_a23 a_a12 a_a22 a_a15 a_a16 v a_a21 a_a24 a_a20 a_we a_a19 a_a14 a_a18 a_a13 ad25 ad22 ad20 ad19 trdy stop v c/be0 cc v cc v ccb v cc v cc cc v cca v cc mfunc1 mfunc3 mfunc4 mfunc5 mfunc6 v cc grst v cc ad16 v cc ccp v b_ce2 b_oe b_iord b_iowr a_iord a_oe a_ce2 a_ce1 b_bvd2(spkr) b_vs2 v cci a_bvd2(spkr) card a card b PCI1420 core pci suspend ri_out/pme c/be2 pdv low-profile quad flat package top view figure 22. pci-to-pc card (16-bit) diagram
23 table 21 and table 22 show the terminal assignments for the cardbus pc card; table 23 and table 24 show the terminal assignments for the 16-bit pc card. table 21 and table 23 show the cardbus pc card and the 16-bit pc card terminals sorted alphanumerically by the associated ghk package terminal number. table 22 and table 24 show the cardbus pc card and the 16-bit pc card terminals sorted alphanumerically by the signal name and its associated terminal numbers. pin e5 is a no connection identification ball. table 21. cardbus pc card signal names by ghk/pdv pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name ghk pdv signal name ghk pdv signal name ghk pdv signal name ghk pdv signal name a4 208 ad12 e3 2 ad10 g19 143 v cc l18 124 a_crst a5 203 c/be1 e6 206 ad13 h1 18 b_cad2 l19 123 a_cad20 a6 199 perr e7 201 v cc h2 17 b_cad0 m1 34 b_cad12 a7 195 irdy e8 194 gnd h3 16 b_ccd1 m2 35 b_cad15 a8 190 ad17 e9 189 ad18 h5 15 ad0 m3 36 b_cad14 a9 185 ad21 e10 183 ad23 h6 11 ad3 m5 38 v ccb a10 180 pclk e11 178 v ccp h14 141 a_cad27 m6 37 b_cad16 a11 175 grst e12 171 ad30 h15 142 a_cad28 m14 115 a_cirdy a12 174 ad28 e13 165 ad25 h17 140 a_ccd2 m15 119 a_cad18 a13 170 ad31 e14 159 mfunc4 h18 139 a_cclkrun m17 120 v cca a14 166 prst e17 155 mfunc1 h19 138 a_cstschg m18 121 a_cad19 a15 162 c/be3 e18 153 gnd j1 19 b_cad1 m19 122 a_cvs2 a16 157 mfunc2 e19 151 clock j2 20 b_cad4 n1 39 b_cc/be1 b5 205 ad14 f1 10 ad4 j3 21 b_cad3 n2 40 b_rsvd b6 200 serr f2 8 ad6 j5 22 gnd n3 41 b_cpar b7 196 trdy f3 7 v cc j6 23 b_cad6 n5 45 b_cstop b8 191 ad16 f5 3 ad9 j14 136 a_cserr n6 42 b_cblock b9 186 ad20 f6 204 ad15 j15 137 a_caudio n14 108 a_cperr b10 181 gnd f7 198 stop j17 135 a_cint n15 113 v cc b11 176 ad27 f8 193 frame j18 134 a_cvs1 n17 116 a_cframe b12 173 ad29 f9 188 ad19 j19 133 a_cad26 n18 117 a_cc/be2 b13 169 req f10 184 ad22 k1 24 b_cad5 n19 118 a_cad17 b14 164 v cc f11 179 ad24 k2 25 b_rsvd p1 43 b_cperr b15 161 mfunc6/clkrun f12 167 gnd k3 26 b_cad7 p2 44 gnd c5 207 gnd f13 160 mfunc5 k5 27 b_cad8 p3 46 b_cgnt c6 202 par f14 152 data k6 28 b_cc/be0 p5 50 b_cirdy c7 197 devsel f15 154 mfunc0 k14 132 a_cad25 p6 48 b_cclk c8 192 c/be2 f17 150 latch k15 131 a_cad24 p7 56 b_cvs2 c9 187 v cc f18 148 v cci k17 130 a_cc/be3 p8 63 b_cc/be3 c10 182 idsel f19 147 a_cad31 k18 129 gnd p9 75 gnd c11 177 ad26 g1 14 ad1 k19 128 a_cad23 p10 80 b_rsvd c12 172 ad11 g2 13 gnd l1 29 b_cad9 p11 84 a_cad2 c13 168 gnt g3 12 ad2 l2 30 b_cad10 p12 89 a_cad6 c14 163 ri_out /pme g5 9 ad5 l3 31 v cc p13 94 a_cc/be0 c15 158 mfunc3 g6 4 ad8 l5 33 b_cad13 p14 100 a_cad12 d1 1 v ccp g14 146 a_rsvd l6 32 b_cad11 p15 107 a_cblock d19 156 suspend g15 149 spkrout l14 127 a_creq p17 111 a_cdevsel e1 6 ad7 g17 145 a_cad30 l15 126 a_cad22 p18 112 a_cclk e2 5 c/be0 g18 144 a_cad29 l17 125 a_cad21 p19 114 a_ctrdy
24 table 21. cardbus pc card signal names by ghk/pdv pin number (continued) pin no. signal name pin no. signal name pin no. signal name pin no. signal name ghk pdv signal name ghk pdv signal name ghk pdv signal name ghk pdv signal name r1 47 b_cdevsel r18 109 a_cstop u14 98 a_cad11 w4 53 b_cad17 r2 49 b_ctrdy r19 110 a_cgnt u15 103 a_cad16 w5 58 b_crst r3 51 b_cframe t1 52 b_cc/be2 v5 57 b_cad20 w6 62 b_cad23 r6 55 b_cad19 t19 105 a_rsvd v6 60 b_cad22 w7 66 b_cad25 r7 61 b_creq u5 54 b_cad18 v7 65 b_cad24 w8 70 b_cserr r8 67 b_cad26 u6 59 b_cad21 v8 69 b_cint w9 71 b_caudio r9 74 b_ccd2 u7 64 v cc v9 72 b_cstschg w10 76 b_cad27 r10 79 b_cad30 u8 68 b_cvs1 v10 77 b_cad28 w11 81 b_cad31 r11 85 a_cad1 u9 73 b_cclkrun v11 82 a_ccd1 w12 86 v cc r12 90 a_cad5 u10 78 b_cad29 v12 87 a_cad4 w13 91 a_rsvd r13 97 a_cad10 u11 83 a_cad0 v13 92 a_cad7 w14 95 a_cad9 r14 102 a_cad14 u12 88 a_cad3 v14 96 gnd w15 99 a_cad13 r17 106 a_cpar u13 93 a_cad8 v15 101 a_cad15 w16 104 a_cc/be1 table 22. cardbus pc card signal names sorted alphabetically signal name pin no. signal name pin no. signal name pin no. signal name pin no. signal name ghk pdv signal name ghk pdv signal name ghk pdv signal name ghk pdv a_cad0 u11 83 a_cad27 h14 141 a_ctrdy p19 114 ad21 a9 185 a_cad1 r11 85 a_cad28 h15 142 a_cvs1 j18 134 ad22 f10 184 a_cad2 p11 84 a_cad29 g18 144 a_cvs2 m19 122 ad23 e10 183 a_cad3 u12 88 a_cad30 g17 145 a_rsvd g14 146 ad24 f11 179 a_cad4 v12 87 a_cad31 f19 147 a_rsvd t19 105 ad25 e13 165 a_cad5 r12 90 a_caudio j15 137 a_rsvd w13 91 ad26 c11 177 a_cad6 p12 89 a_cblock p15 107 ad0 h5 15 ad27 b11 176 a_cad7 v13 92 a_cc/be0 p13 94 ad1 g1 14 ad28 a12 174 a_cad8 u13 93 a_cc/be1 w16 104 ad2 g3 12 ad29 b12 173 a_cad9 w14 95 a_cc/be2 n18 117 ad3 h6 11 ad30 e12 171 a_cad10 r13 97 a_cc/be3 k17 130 ad4 f1 10 ad31 a13 170 a_cad11 u14 98 a_ccd1 v11 82 ad5 g5 9 b_cad0 h2 17 a_cad12 p14 100 a_ccd2 h17 140 ad6 f2 8 b_cad1 j1 19 a_cad13 w15 99 a_cclk p18 112 ad7 e1 6 b_cad2 h1 18 a_cad14 r14 102 a_cclkrun h18 139 ad8 g6 4 b_cad3 j3 21 a_cad15 v15 101 a_cdevsel p17 111 ad9 f5 3 b_cad4 j2 20 a_cad16 u15 103 a_cframe n17 116 ad10 e3 2 b_cad5 k1 24 a_cad17 n19 118 a_cgnt r19 110 ad11 c12 172 b_cad6 j6 23 a_cad18 m15 119 a_cint j17 135 ad12 a4 208 b_cad7 k3 26 a_cad19 m18 121 a_cirdy m14 115 ad13 e6 206 b_cad8 k5 27 a_cad20 l19 123 a_cpar r17 106 ad14 b5 205 b_cad9 l1 29 a_cad21 l17 125 a_cperr n14 108 ad15 f6 204 b_cad10 l2 30 a_cad22 l15 126 a_creq l14 127 ad16 b8 191 b_cad11 l6 32 a_cad23 k19 128 a_crst l18 124 ad17 a8 190 b_cad12 m1 34 a_cad24 k15 131 a_cserr j14 136 ad18 e9 189 b_cad13 l5 33 a_cad25 k14 132 a_cstop r18 109 ad19 f9 188 b_cad14 m3 36 a_cad26 j19 133 a_cstschg h19 138 ad20 b9 186 b_cad15 m2 35
25 table 22. cardbus pc card signal names sorted alphabetically (continued) signal name pin no. signal name pin no. signal name pin no. signal name pin no. signal name ghk pdv signal name ghk pdv signal name ghk pdv signal name ghk pdv b_cad16 m6 37 b_cclkrun u9 73 devsel c7 197 par c6 202 b_cad17 w4 53 b_cdevsel r1 47 frame f8 193 pclk a10 180 b_cad18 u5 54 b_cframe r3 51 gnd b10 181 perr a6 199 b_cad19 r6 55 b_cgnt p3 46 gnd c5 207 prst a14 166 b_cad20 v5 57 b_cint v8 69 gnd e8 194 req b13 169 b_cad21 u6 59 b_cirdy p5 50 gnd e18 153 ri_out /pme c14 163 b_cad22 v6 60 b_cpar n3 41 gnd f12 167 serr b6 200 b_cad23 w6 62 b_cperr p1 43 gnd g2 13 spkrout g15 149 b_cad24 v7 65 b_creq r7 61 gnd j5 22 stop f7 198 b_cad25 w7 66 b_crst w5 58 gnd k18 129 suspend d19 156 b_cad26 r8 67 b_cserr w8 70 gnd p2 44 trdy b7 196 b_cad27 w10 76 b_cstop n5 45 gnd p9 75 v cc b14 164 b_cad28 v10 77 b_cstschg v9 72 gnd v14 96 v cc c9 187 b_cad29 u10 78 b_ctrdy r2 49 gnt c13 168 v cc e7 201 b_cad30 r10 79 b_cvs1 u8 68 grst a11 175 v cc f3 7 b_cad31 w11 81 b_cvs2 p7 56 idsel c10 182 v cc g19 143 b_caudio w9 71 b_rsvd k2 25 irdy a7 195 v cc l3 31 b_cblock n6 42 b_rsvd n2 40 latch f17 150 v cc n15 113 b_cc/be0 k6 28 b_rsvd p10 80 mfunc0 f15 154 v cc u7 64 b_cc/be1 n1 39 c/be0 e2 5 mfunc1 e17 155 v cc w12 86 b_cc/be2 t1 52 c/be1 a5 203 mfunc2 a16 157 v cca m17 120 b_cc/be3 p8 63 c/be2 c8 192 mfunc3 c15 158 v ccb m5 38 b_ccd1 h3 16 c/be3 a15 162 mfunc4 e14 159 v cci f18 148 b_ccd2 r9 74 clock e19 151 mfunc5 f13 160 v ccp d1 1 b_cclk p6 48 data f14 152 mfunc6/clkrun b15 161 v ccp e11 178 table 23. 16-bit pc card signal names by ghk/pdv pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name ghk pdv signal name ghk pdv signal name ghk pdv signal name ghk pdv signal name a4 208 ad12 b7 196 trdy c11 177 ad26 e11 178 v ccp a5 203 c/be1 b8 191 ad16 c12 172 ad11 e12 171 ad30 a6 199 perr b9 186 ad20 c13 168 gnt e13 165 ad25 a7 195 irdy b10 181 gnd c14 163 ri_out /pme e14 159 mfunc4 a8 190 ad17 b11 176 ad27 c15 158 mfunc3 e17 155 mfunc1 a9 185 ad21 b12 173 ad29 d1 1 v ccp e18 153 gnd a10 180 pclk b13 169 req d19 156 suspend e19 151 clock a11 175 grst b14 164 v cc e1 6 ad7 f1 10 ad4 a12 174 ad28 b15 161 mfunc6 e2 5 c/be0 f2 8 ad6 a13 170 ad31 c5 207 gnd e3 2 ad10 f3 7 v cc a14 166 prst c6 202 par e6 206 ad13 f5 3 ad9 a15 162 c/be3 c7 197 devsel e7 201 v cc f6 204 ad15 a16 157 mfunc2 c8 192 c/be2 e8 194 gnd f7 198 stop b5 205 ad14 c9 187 v cc e9 189 ad18 f8 193 frame b6 200 serr c10 182 idsel e10 183 ad23 f9 188 ad19
26 table 23. 16-bit pc card signal names by ghk/pdv pin number (continued) pin no. signal name pin no. signal pin no. signal pin no. signal name ghk pdv signal name ghk pdv name ghk pdv name ghk pdv signal name f10 184 ad22 j18 134 a_vs1 n14 108 a_a14 t1 52 b_a12 f11 179 ad24 j19 133 a_a0 n15 113 v cc t19 105 a_a18 f12 167 gnd k1 24 b_d6 n17 116 a_a23 u5 54 b_a7 f13 160 mfunc5 k2 25 b_d14 n18 117 a_a12 u6 59 b_a5 f14 152 data k3 26 b_d7 n19 118 a_a24 u7 64 v cc f15 154 mfunc0 k5 27 b_d15 p1 43 b_a14 u8 68 b_vs1 f17 150 latch k6 28 b_ce1 p2 44 gnd u9 73 b_wp(iois16 ) f18 148 v cci k14 132 a_a1 p3 46 b_we u10 78 b_d1 f19 147 a_d10 k15 131 a_a2 p5 50 b_a15 u11 83 a_d3 g1 14 ad1 k17 130 a_reg p6 48 b_a16 u12 88 a_d5 g2 13 gnd k18 129 gnd p7 56 b_vs2 u13 93 a_d15 g3 12 ad2 k19 128 a_a3 p8 63 b_reg u14 98 a_oe g5 9 ad5 l1 29 b_a10 p9 75 gnd u15 103 a_a17 g6 4 ad8 l2 30 b_ce2 p10 80 b_d2 v5 57 b_a6 g14 146 a_d2 l3 31 v cc p11 84 a_d11 v6 60 b_a4 g15 149 spkrout l5 33 b_iord p12 89 a_d13 v7 65 b_a2 g17 145 a_d9 l6 32 b_oe p13 94 a_ce1 v8 69 b_ready(ireq ) g18 144 a_d1 l14 127 a_inpack p14 100 a_a11 v9 72 b_bvd1(stschg /r1 ) g19 143 v cc l15 126 a_a4 p15 107 a_a19 v10 77 b_d8 h1 18 b_d11 l17 125 a_a5 p17 111 a_a21 v11 82 a_cd1 h2 17 b_d3 l18 124 a_reset p18 112 a_a16 v12 87 a_d12 h3 16 b_cd1 l19 123 a_a6 p19 114 a_a22 v13 92 a_d7 h5 15 ad0 m1 34 b_a11 r1 47 b_a21 v14 96 gnd h6 11 ad3 m2 35 b_iowr r2 49 b_a22 v15 101 a_iowr h14 141 a_d0 m3 36 b_a9 r3 51 b_a23 w4 53 b_a24 h15 142 a_d8 m5 38 v ccb r6 55 b_a25 w5 58 b_reset h17 140 a_cd2 m6 37 b_a17 r7 61 b_inpack w6 62 b_a3 h18 139 a_wp(iois16 ) m14 115 a_a15 r8 67 b_a0 w7 66 b_a1 h19 138 a_bvd1(stschg /r1 ) m15 119 a_a7 r9 74 b_cd2 w8 70 b_wait j1 19 b_d4 m17 120 v cca r10 79 b_d9 w9 71 b_bvd2(spkr ) j2 20 b_d12 m18 121 a_a25 r11 85 a_d4 w10 76 b_d0 j3 21 b_d5 m19 122 a_vs2 r12 90 a_d6 w11 81 b_d10 j5 22 gnd n1 39 b_a8 r13 97 a_ce2 w12 86 v cc j6 23 b_d13 n2 40 b_a18 r14 102 a_a9 w13 91 a_d14 j14 136 a_wait n3 41 b_a13 r17 106 a_a13 w14 95 a_a10 j15 137 a_bvd2(spkr ) n5 45 b_a20 r18 109 a_a20 w15 99 a_iord j17 135 a_ready(ireq ) n6 42 b_a19 r19 110 a_we w16 104 a_a8
27 table 24. 16-bit pc card signal names sorted alphabetically signal name pin no. signal name pin no. signal name pin no. signal name pin no. signal name ghk pdv signal name ghk pdv signal name ghk pdv signal name ghk pdv a_a0 j19 133 a_d11 p11 84 ad26 c11 177 b_d5 j3 21 a_a1 k14 132 a_d12 v12 87 ad27 b11 176 b_d6 k1 24 a_a2 k15 131 a_d13 p12 89 ad28 a12 174 b_d7 k3 26 a_a3 k19 128 a_d14 w13 91 ad29 b12 173 b_d8 v10 77 a_a4 l15 126 a_d15 u13 93 ad30 e12 171 b_d9 r10 79 a_a5 l17 125 a_inpack l14 127 ad31 a13 170 b_d10 w11 81 a_a6 l19 123 a_iord w15 99 b_a0 r8 67 b_d11 h1 18 a_a7 m15 119 a_iowr v15 101 b_a1 w7 66 b_d12 j2 20 a_a8 w16 104 a_oe u14 98 b_a2 v7 65 b_d13 j6 23 a_a9 r14 102 a_ready(ireq ) j17 135 b_a3 w6 62 b_d14 k2 25 a_a10 w14 95 a_reg k17 130 b_a4 v6 60 b_d15 k5 27 a_a11 p14 100 a_reset l18 124 b_a5 u6 59 b_inpack r7 61 a_a12 n18 117 a_vs1 j18 134 b_a6 v5 57 b_iord l5 33 a_a13 r17 106 a_vs2 m19 122 b_a7 u5 54 b_iowr m2 35 a_a14 n14 108 a_wait j14 136 b_a8 n1 39 b_oe l6 32 a_a15 m14 115 a_we r19 110 b_a9 m3 36 b_ready(ireq ) v8 69 a_a16 p18 112 a_wp(iois16 ) h18 139 b_a10 l1 29 b_reg p8 63 a_a17 u15 103 ad0 h5 15 b_a11 m1 34 b_reset w5 58 a_a18 t19 105 ad1 g1 14 b_a12 t1 52 b_vs1 u8 68 a_a19 p15 107 ad2 g3 12 b_a13 n3 41 b_vs2 p7 56 a_a20 r18 109 ad3 h6 11 b_a14 p1 43 b_wait w8 70 a_a21 p17 111 ad4 f1 10 b_a15 p5 50 b_we p3 46 a_a22 p19 114 ad5 g5 9 b_a16 p6 48 b_wp(iois16 ) u9 73 a_a23 n17 116 ad6 f2 8 b_a17 m6 37 c/be0 e2 5 a_a24 n19 118 ad7 e1 6 b_a18 n2 40 c/be1 a5 203 a_a25 m18 121 ad8 g6 4 b_a19 n6 42 c/be2 c8 192 a_bvd1(stschg /r1 ) h19 138 ad9 f5 3 b_a20 n5 45 c/be3 a15 162 a_bvd2(spkr ) j15 137 ad10 e3 2 b_a21 r1 47 clock e19 151 a_cd1 v11 82 ad11 c12 172 b_a22 r2 49 data f14 152 a_cd2 h17 140 ad12 a4 208 b_a23 r3 51 devsel c7 197 a_ce1 p13 94 ad13 e6 206 b_a24 w4 53 frame f8 193 a_ce2 r13 97 ad14 b5 205 b_a25 r6 55 gnd b10 181 a_d0 h14 141 ad15 f6 204 b_bvd1(stschg /r1 ) v9 72 gnd c5 207 a_d1 g18 144 ad16 b8 191 b_bvd2(spkr ) w9 71 gnd e8 194 a_d2 g14 146 ad17 a8 190 b_cd1 h3 16 gnd e18 153 a_d3 u11 83 ad18 e9 189 b_cd2 r9 74 gnd f12 167 a_d4 r11 85 ad19 f9 188 b_ce1 k6 28 gnd g2 13 a_d5 u12 88 ad20 b9 186 b_ce2 l2 30 gnd j5 22 a_d6 r12 90 ad21 a9 185 b_d0 w10 76 gnd k18 129 a_d7 v13 92 ad22 f10 184 b_d1 u10 78 gnd p2 44 a_d8 h15 142 ad23 e10 183 b_d2 p10 80 gnd p9 75 a_d9 g17 145 ad24 f11 179 b_d3 h2 17 gnd v14 96 a_d10 f19 147 ad25 e13 165 b_d4 j1 19 gnt c13 168
28 table 24. 16-bit pc card signal names sorted alphabetically (continued) signal name pin no. signal name pin no. signal name pin no. signal name pin no. signal name ghk pdv signal name ghk pdv signal name ghk pdv signal name ghk pdv grst a11 175 mfunc5 f13 160 spkrout g15 149 v cc l3 31 idsel c10 182 mfunc6 b15 161 stop f7 198 v cc n15 113 irdy a7 195 par c6 202 suspend d19 156 v cc u7 64 latch f17 150 pclk a10 180 trdy b7 196 v cc w12 86 mfunc0 f15 154 perr a6 199 v cc b14 164 v cca m17 120 mfunc1 e17 155 prst a14 166 v cc c9 187 v ccb m5 38 mfunc2 a16 157 req b13 169 v cc e7 201 v cci f18 148 mfunc3 c15 158 ri_out /pme c14 163 v cc f3 7 v ccp d1 1 mfunc4 e14 159 serr b6 200 v cc g19 143 v ccp e11 178 the terminals are grouped in tables by functionality, such as pci system function, power-supply function, etc. the terminal numbers are also listed for convenient reference. table 25. power supply terminal name no. description name pdv ghk gnd 13, 22, 44, 75, 96, 129, 153, 167, 181, 194, 207 b10, c5, e8, e18, f12, g2, j5, k18, p2, p9, v14 device ground terminals v cc 7, 31, 64, 86, 113, 143, 164, 187, 201 b14, c9, e7, f3, g19, l3, n15, u7, w12 power supply terminal for core logic (3.3 v) v cca 120 m17 clamp voltage for pc card a interface. matches card a signaling environment, 5 v or 3.3 v. v ccb 38 m5 clamp voltage for pc card b interface. matches card b signaling environment, 5 v or 3.3 v. v cci 148 f18 clamp voltage for interrupt subsystem interface and miscellaneous i/o, 5 v or 3.3 v v ccp 1, 178 d1, e11 clamp voltage for pci signaling, 5 v or 3.3 v table 26. pc card power switch terminal name no. i/o description name pdv ghk clock 151 e19 i/o power switch clock. information on the data line is sampled at the rising edge of clock. clock defaults to an input, but can be changed to a PCI1420 output by using bit 27 (p2cclk) in the system control register (see section 4.29). the tps2206 defines the maximum frequency of this signal to be 2 mhz. if a system design defines this terminal as an output, then this terminal requires an external pulldown resistor. the frequency of the PCI1420 output clock is derived from dividing the pci clk by 36. data 152 f14 o power switch data. data is used to serially communicate socket power control information to the power switch. latch 150 f17 o power switch latch. latch is asserted by the PCI1420 to indicate to the power switch that the data on the data line is valid. when a pulldown resistor is implemented on this terminal, the mfunc1 and mfunc4 terminals provide the serial eeprom sda and scl interface.
29 table 27. pci system terminal name no. i/o description name pdv ghk grst 175 a11 i global reset. when the global reset is asserted, the grst signal causes the PCI1420 to place all output buffers in a high-impedance state and reset all internal registers. when grst is asserted, the device is completely in its default state. for systems that require wake-up from d3, grst will normally be asserted only during initial boot. prst should be asserted following initial boot so that pme context is retained when transitioning from d3 to d0. for systems that do not require wake-up from d3, grst should be tied to prst . when the suspend mode is enabled, the device is protected from the grst , and the internal registers are preserved. all outputs are placed in a high-impedance state, but the contents of the registers are preserved. pclk 180 a10 i pci bus clock. pclk provides timing for all transactions on the pci bus. all pci signals are sampled at the rising edge of pclk. prst 166 a14 i pci reset. when the pci bus reset is asserted, prst causes the PCI1420 to place all output buffers in a high-impedance state and reset internal registers. when prst is asserted, the device is completely nonfunctional. after prst is deasserted, the PCI1420 is in a default state. when the suspend mode is enabled, the device is protected from the prst , and the internal registers are preserved. all outputs are placed in a high-impedance state, but the contents of the registers are preserved.
210 table 28. pci address and data terminal name no. i/o description name pdv ghk ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 170 171 173 174 176 177 165 179 183 184 185 186 188 189 190 191 204 205 206 208 172 2 3 4 6 8 9 10 11 12 14 15 a13 e12 b12 a12 b11 c11 e13 f11 e10 f10 a9 b9 f9 e9 a8 b8 f6 b5 e6 a4 c12 e3 f5 g6 e1 f2 g5 f1 h6 g3 g1 h5 i/o pci address/data bus. these signals make up the multiplexed pci address and data bus on the primary interface. during the address phase of a primary bus pci cycle, ad31ad0 contain a 32-bit address or other destination information. during the data phase, ad31ad0 contain data. c/be3 c/be2 c/be1 c/be0 162 192 203 5 a15 c8 a5 e2 i/o pci bus commands and byte enables. these signals are multiplexed on the same pci terminals. during the address phase of a primary bus pci cycle, c/be3 c/be0 define the bus command. during the data phase, this 4-bit bus is used as byte enables. the byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. c/be0 applies to byte 0 (ad7ad0), c/be1 applies to byte 1 (ad15ad8), c/be2 applies to byte 2 (ad23ad16), and c/be3 applies to byte 3 (ad31ad24). par 202 c6 i/o pci bus parity. in all pci bus read and write cycles, the PCI1420 calculates even parity across the ad31ad0 and c/be3 c/be0 buses. as an initiator during pci cycles, the PCI1420 outputs this parity indicator with a one-pclk delay. as a target during pci cycles, the calculated parity is compared to the initiator's parity indicator. a compare error results in the assertion of a parity error (perr ).
211 table 29. pci interface control terminal name no. i/o description name pdv ghk devsel 197 c7 i/o pci device select. the PCI1420 asserts devsel to claim a pci cycle as the target device. as a pci initiator on the bus, the PCI1420 monitors devsel until a target responds. if no target responds before timeout occurs, then the PCI1420 terminates the cycle with an initiator abort. frame 193 f8 i/o pci cycle frame. frame is driven by the initiator of a bus cycle. frame is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. when frame is deasserted, the pci bus transaction is in the final data phase. gnt 168 c13 i pci bus grant. gnt is driven by the pci bus arbiter to grant the PCI1420 access to the pci bus after the current data transaction has completed. gnt may or may not follow a pci bus request, depending on the pci bus parking algorithm. idsel 182 c10 i initialization device select. idsel selects the PCI1420 during configuration space accesses. idsel can be connected to one of the upper 24 pci address lines on the pci bus. irdy 195 a7 i/o pci initiator ready. irdy indicates the pci bus initiator's ability to complete the current data phase of the transaction. a data phase is completed on a rising edge of pclk where both irdy and trdy are asserted. until irdy and trdy are both sampled asserted, wait states are inserted. perr 199 a6 i/o pci parity error indicator. perr is driven by a pci device to indicate that calculated parity does not match par when perr is enabled through bit 6 of the command register (see section 4.4). req 169 b13 o pci bus request. req is asserted by the PCI1420 to request access to the pci bus as an initiator. serr 200 b6 o pci system error. serr is an output that is pulsed from the PCI1420 when enabled through bit 8 of the command register (see section 4.4) indicating a system error has occurred. the PCI1420 need not be the target of the pci cycle to assert this signal. when serr is enabled in the command register, this signal also pulses, indicating that an address parity error has occurred on a cardbus interface. stop 198 f7 i/o pci cycle stop signal. stop is driven by a pci target to request the initiator to stop the current pci bus transaction. stop is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. trdy 196 b7 i/o pci target ready. trdy indicates the primary bus target's ability to complete the current data phase of the transaction. a data phase is completed on a rising edge of pclk when both irdy and trdy are asserted. until both irdy and trdy are asserted, wait states are inserted.
212 table 210. multifunction and miscellaneous pins terminal name no. i/o description name pdv ghk mfunc0 154 f15 i/o multifunction terminal 0. mfunc0 can be configured as parallel pci interrupt inta , gpi0, gpo0, socket activity led output, zv switching outputs, cardbus audio pwm, gpe , or a parallel irq. see section 4.30, multifunction routing register , for configuration details. mfunc1 155 e17 i/o multifunction terminal 1. mfunc1 can be configured as parallel pci interrupt intb , gpi1, gpo1, socket activity led output, zv switching outputs, cardbus audio pwm, gpe , or a parallel irq. see section 4.30, multifunction routing register , for configuration details. serial data (sda). when latch is detected low after a pci reset, the mfunc1 terminal provides the sda signaling for the serial bus interface. the two-pin serial interface loads the subsystem identification and other register defaults from an eeprom after a pci reset. see section 3.6.1, serial bus interface implementation , for details on other serial bus applications. mfunc2 157 a16 i/o multifunction terminal 2. mfunc2 can be configured as pc/pci dma request, gpi2, gpo2, socket activity led output, zv switching outputs, cardbus audio pwm, gpe , ri_out , or a parallel irq. see section 4.30, multifunction routing register , for configuration details. mfunc3 158 c15 i/o multifunction terminal 3. mfunc3 can be configured as a parallel irq or the serialized interrupt signal irqser. see section 4.30, multifunction routing register , for configuration details. mfunc4 159 e14 i/o multifunction terminal 4. mfunc4 can be configured as pci lock , gpi3, gpo3, socket activity led output, zv switching outputs, cardbus audio pwm, gpe , ri_out , or a parallel irq. see section 4.30, multifunction routing register , for configuration details. serial clock (scl). when latch is detected low after a pci reset, the mfunc4 terminal provides the scl signaling for the serial bus interface. the two-pin serial interface loads the subsystem identification and other register defaults from an eeprom after a pci reset. see section 3.6.1, serial bus interface implementation , for details on other serial bus applications. mfunc5 160 f13 i/o multifunction terminal 5. mfunc5 can be configured as pc/pci dma grant, gpi4, gpo4, socket activity led output, zv switching outputs, cardbus audio pwm, gpe , or a parallel irq. see section 4.30, multifunction routing register , for configuration details. mfunc6 161 b15 i/o multifunction terminal 6. mfunc6 can be configured as a pci clkrun or a parallel irq. see section 4.30, multifunction routing register , for configuration details. ri_out /pme 163 c14 o ring indicate out and power management event output. terminal provides an output for ring-indicate or pme signals. spkrout 149 g15 o speaker output. spkrout is the output to the host system that can carry spkr or caudio through the PCI1420 from the pc card interface. spkrout is driven as the exclusive-or combination of card spkr //caudio inputs. suspend 156 d19 i suspend. suspend protects the internal registers from clearing when the grst or prst signal is asserted. see section 3.8.4, suspend mode , for details.
213 table 211. 16-bit pc card address and data (slots a and b) terminal number i/o description name slot a 2 slot b 3 i/o description pdv ghk pdv ghk a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 121 118 116 114 111 109 107 105 103 112 115 108 106 117 100 95 102 104 119 123 125 126 128 131 132 133 m18 n19 n17 p19 p17 r18 p15 t19 u15 p18 m14 n14 r17 n18 p14 w14 r14 w16 m15 l19 l17 l15 k19 k15 k14 j19 55 53 51 49 47 45 42 40 37 48 50 43 41 52 34 29 36 39 54 57 59 60 62 65 66 67 r6 w4 r3 r2 r1 n5 n6 n2 m6 p6 p5 p1 n3 t1 m1 l1 m3 n1 u5 v5 u6 v6 w6 v7 w7 r8 o pc card address. 16-bit pc card address lines. a25 is the most significant bit. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 93 91 89 87 84 147 145 142 92 90 88 85 83 146 144 141 u13 w13 p12 v12 p11 f19 g17 h15 v13 r12 u12 r11 u11 g14 g18 h14 27 25 23 20 18 81 79 77 26 24 21 19 17 80 78 76 k5 k2 j6 j2 h1 w11 r10 v10 k3 k1 j3 j1 h2 p10 u10 w10 i/o pc card data. 16-bit pc card data lines. d15 is the most significant bit. 2 terminal name for slot a is preceded with a_. for example, the full name for terminals 121 and m18 are a_a25. 3 terminal name for slot b is preceded with b_. for example, the full name for terminals 55 and r6 are b_a25.
214 table 212. 16-bit pc card interface control (slots a and b) terminal number i/o description name slot a 2 slot b 3 i/o description pdv ghk pdv ghk bvd1 (stschg /ri ) 138 h19 72 v9 i battery voltage detect 1. bvd1 is generated by 16-bit memory pc cards that include batteries. bvd1 is used with bvd2 as an indication of the condition of the batteries on a memory pc card. both bvd1 and bvd2 are high when the battery is good. when bvd2 is low and bvd1 is high, the battery is weak and should be replaced. when bvd1 is low, the battery is no longer serviceable and the data in the memory pc card is lost. see section 5.6, exca card status-change-interrupt configuration register , for enable bits. see section 5.5, exca card status-change register , and section 5.2, exca interface status register , for the status bits for this signal. status change. stschg is used to alert the system to a change in the ready, write protect, or battery voltage dead condition of a 16-bit i/o pc card. ring indicate. ri is used by 16-bit modem cards to indicate a ring detection. bvd2 (spkr ) 137 j15 71 w9 i battery voltage detect 2. bvd2 is generated by 16-bit memory pc cards that include batteries. bvd2 is used with bvd1 as an indication of the condition of the batteries on a memory pc card. both bvd1 and bvd2 are high when the battery is good. when bvd2 is low and bvd1 is high, the battery is weak and should be replaced. when bvd1 is low, the battery is no longer serviceable and the data in the memory pc card is lost. see section 5.6, exca card status-change-interrupt configuration register , for enable bits. see section 5.5, exca card status-change register , and section 5.2, exca interface status register , for the status bits for this signal. speaker. spkr is an optional binary audio signal available only when the card and socket have been configured for the 16-bit i/o interface. the audio signals from cards a and b are combined by the PCI1420 and are output on spkrout. dma request. bvd2 can be used as the dma request signal during dma operations to a 16-bit pc card that supports dma. the pc card asserts bvd2 to indicate a request for a dma operation. cd1 cd2 82 140 v11 h17 16 74 h3 r9 i card detect 1 and card detect 2. cd1 and cd2 are internally connected to ground on the pc card. when a pc card is inserted into a socket, cd1 and cd2 are pulled low. for signal status, see section 5.2, exca interface status register . ce1 ce2 94 97 p13 r13 28 30 k6 l2 o card enable 1 and card enable 2. ce1 and ce2 enable even- and odd-numbered address bytes. ce1 enables even-numbered address bytes, and ce2 enables odd-numbered address bytes. inpack 127 l14 61 r7 i input acknowledge. inpack is asserted by the pc card when it can respond to an i/o read cycle at the current address. dma request. inpack can be used as the dma request signal during dma operations from a 16-bit pc card that supports dma. if it is used as a strobe, then the pc card asserts this signal to indicate a request for a dma operation. iord 99 w15 33 l5 o i/o read. iord is asserted by the PCI1420 to enable 16-bit i/o pc card data output during host i/o read cycles. dma write. iord is used as the dma write strobe during dma operations from a 16-bit pc card that supports dma. the PCI1420 asserts iord during dma transfers from the pc card to host memory. iowr 101 v15 35 m2 o i/o write. iowr is driven low by the PCI1420 to strobe write data into 16-bit i/o pc cards during host i/o write cycles. dma read. iowr is used as the dma write strobe during dma operations from a 16-bit pc card that supports dma. the PCI1420 asserts iowr during transfers from host memory to the pc card. 2 terminal name for slot a is preceded with a_. for example, the full name for terminals 127 and l14 are a_inpack . 3 terminal name for slot b is preceded with b_. for example, the full name for terminals 61 and r7 are b_inpack .
215 table 212. 16-bit pc card interface control (slots a and b) (continued) terminal number i/o description name slot a 2 slot b 3 i/o description pdv ghk pdv ghk oe 98 u14 32 l6 o output enable. oe is driven low by the PCI1420 to enable 16-bit memory pc card data output during host memory read cycles. dma terminal count. oe is used as terminal count (tc) during dma operations to a 16-bit pc card that supports dma. the PCI1420 asserts oe to indicate tc for a dma write operation. ready (ireq ) 135 j17 69 v8 i ready. the ready function is provided by ready when the 16-bit pc card and the host socket are configured for the memory-only interface. ready is driven low by the 16-bit memory pc cards to indicate that the memory card circuits are busy processing a previous write command. ready is driven high when the 16-bit memory pc card is ready to accept a new data transfer command. interrupt request. ireq is asserted by a 16-bit i/o pc card to indicate to the host that a device on the 16-bit i /o pc card requires service by the host software. ireq is high (deasserted) when no interrupt is requested. reg 130 k17 63 p8 o attribute memory select. reg remains high for all common memory accesses. when reg is asserted, access is limited to attribute memory (oe or we active) and to the i/o space (iord or iowr active). attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. dma acknowledge. reg is used as a dma acknowledge (dack ) during dma operations to a 16-bit pc card that supports dma. the PCI1420 asserts reg to indicate a dma operation. reg is used in conjunction with the dma read (iowr ) or dma write (iord ) strobes to transfer data. reset 124 l18 58 w5 o pc card reset. reset forces a hard reset to a 16-bit pc card. wait 136 j14 70 w8 i bus cycle wait. wait is driven by a 16-bit pc card to extend the completion of the memory or i/o cycle in progress. we 110 r19 46 p3 o write enable. we is used to strobe memory write data into 16-bit memory pc cards. we is also used for memory pc cards that employ programmable memory technologies. dma terminal count. we is used as tc during dma operations to a 16-bit pc card that supports dma. the PCI1420 asserts we to indicate tc for a dma read operation. wp (iois16 ) 139 h18 73 u9 i write protect. wp applies to 16-bit memory pc cards. wp reflects the status of the write-protect switch on 16-bit memory pc cards. for 16-bit i/o cards, wp is used for the 16-bit port (iois16 ) function. i/o is 16 bits. iois16 applies to 16-bit i/o pc cards. iois16 is asserted by the 16-bit pc card when the address on the bus corresponds to an address to which the 16-bit pc card responds, and the i/o port that is addressed is capable of 16-bit accesses. dma request. wp can be used as the dma request signal during dma operations to a 16-bit pc card that supports dma. if used, then the pc card asserts wp to indicate a request for a dma operation. vs1 vs2 134 122 j18 m19 68 56 u8 p7 i/o voltage sense 1 and voltage sense 2. vs1 and vs2 , when used in conjunction with each other, determine the operating voltage of the pc card. 2 terminal name for slot a is preceded with a_. for example, the full name for terminals 110 and r19 are a_we . 3 terminal name for slot b is preceded with b_. for example, the full name for terminals 46 and p3 are b_we .
216 table 213. cardbus pc card interface system (slots a and b) terminal number i/o description name slot a 2 slot b 3 i/o description pdv ghk pdv ghk cclk 112 p18 48 p6 o cardbus clock. cclk provides synchronous timing for all transactions on the cardbus interface. all signals except crst , cclkrun , cint , cstschg, caudio, ccd2 , ccd1 , cvs2, and cvs1 are sampled on the rising edge of cclk, and all timing parameters are defined with the rising edge of this signal. cclk operates at the pci bus clock frequency, but it can be stopped in the low state or slowed down for power savings. cclkrun 139 h18 73 u9 o cardbus clock run. cclkrun is used by a cardbus pc card to request an increase in the cclk frequency, and by the PCI1420 to indicate that the cclk frequency is going to be decreased. crst 124 l18 58 w5 i/o cardbus reset. crst brings cardbus pc card-specific registers, sequencers, and signals to a known state. when crst is asserted, all cardbus pc card signals are placed in a high-impedance state, and the PCI1420 drives these signals to a valid logic level. assertion can be asynchronous to cclk, but deassertion must be synchronous to cclk. 2 terminal name for slot a is preceded with a_. for example, the full name for terminals 112 and p18 are a_cclk. 3 terminal name for slot b is preceded with b_. for example, the full name for terminals 48 and p6 are b_cclk.
217 table 214. cardbus pc card address and data (slots a and b) terminal number i/o description name slot a 2 slot b 3 i/o description pdv ghk pdv ghk cad31 cad30 cad29 cad28 cad27 cad26 cad25 cad24 cad23 cad22 cad21 cad20 cad19 cad18 cad17 cad16 cad15 cad14 cad13 cad12 cad11 cad10 cad9 cad8 cad7 cad6 cad5 cad4 cad3 cad2 cad1 cad0 147 145 144 142 141 133 132 131 128 126 125 123 121 119 118 103 101 102 99 100 98 97 95 93 92 89 90 87 88 84 85 83 f19 g17 g18 h15 h14 j19 k14 k15 k19 l15 l17 l19 m18 m15 n19 u15 v15 r14 w15 p14 u14 r13 w14 u13 v13 p12 r12 v12 u12 p11 r11 u11 81 79 78 77 76 67 66 65 62 60 59 57 55 54 53 37 35 36 33 34 32 30 29 27 26 23 24 20 21 18 19 17 w11 r10 u10 v10 w10 r8 w7 v7 w6 v6 u6 v5 r6 u5 w4 m6 m2 m3 l5 m1 l6 l2 l1 k5 k3 j6 k1 j2 j3 h1 j1 h2 i/o cardbus address and data. these signals make up the multiplexed cardbus address and data bus on the cardbus interface. during the address phase of a cardbus cycle, cad31cad0 contain a 32-bit address. during the data phase of a cardbus cycle, cad31cad0 contain data. cad31 is the most significant bit. cc/be3 cc/be2 cc/be1 cc/be0 130 117 104 94 k17 n18 w16 p13 63 52 39 28 p8 t1 n1 k6 i/o cardbus bus commands and byte enables. cc/be3 cc/be0 are multiplexed on the same cardbus terminals. during the address phase of a cardbus cycle, cc/be3 cc/be0 define the bus command. during the data phase, this 4-bit bus is used as byte enables. the byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. cc/be0 applies to byte 0 (cad7cad0), cc/be1 applies to byte 1 (cad15cad8), cc/be2 applies to byte 2 (cad23cad8), and cc/be3 applies to byte 3 (cad31cad24). cpar 106 r17 41 n3 i/o cardbus parity. in all cardbus read and write cycles, the PCI1420 calculates even parity across the cad and cc/be buses. as an initiator during cardbus cycles, the PCI1420 outputs cpar with a one-cclk delay. as a target during cardbus cycles, the calculated parity is compared to the initiator's parity indicator; a compare error results in a parity error assertion. 2 terminal name for slot a is preceded with a_. for example, the full name for terminals 106 and r17 are a_cpar. 3 terminal name for slot b is preceded with b_. for example, the full name for terminals 41 and n3 are b_cpar.
218 table 215. cardbus pc card interface control (slots a and b) terminal number i/o description name slot a 2 slot b 3 i/o description pdv ghk pdv ghk caudio 137 j15 71 w9 i cardbus audio. caudio is a digital input signal from a pc card to the system speaker. the PCI1420 supports the binary audio mode and outputs a binary signal from the card to spkrout. cblock 107 p15 42 n6 i/o cardbus lock. cblock is used to gain exclusive access to a target. ccd1 82 v11 16 h3 i cardbus detect 1 and cardbus detect 2. ccd1 and ccd2 are used in conjunction with cvs1 and cvs2 to identify card insertion and interrogate cards to determine the ccd2 140 h17 74 r9 i w ith cvs1 an d cvs2 t o id en tif y car d i nser ti on an d i n t erroga t e car d s t o d e t erm i ne th e operating voltage and card type. cdevsel 111 p17 47 r1 i/o cardbus device select. the PCI1420 asserts cdevsel to claim a cardbus cycle as the target device. as a cardbus initiator on the bus, the PCI1420 monitors cdevsel until a target responds. if no target responds before timeout occurs, then the PCI1420 terminates the cycle with an initiator abort. cframe 116 n17 51 r3 i/o cardbus cycle frame. cframe is driven by the initiator of a cardbus bus cycle. cframe is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. when cframe is deasserted, the cardbus bus transaction is in the final data phase. cgnt 110 r19 46 p3 i cardbus bus grant. cgnt is driven by the PCI1420 to grant a cardbus pc card access to the cardbus bus after the current data transaction has been completed. cint 135 j17 69 v8 i cardbus interrupt. cint is asserted low by a cardbus pc card to request interrupt servicing from the host. cirdy 115 m14 50 p5 i/o cardbus initiator ready. cirdy indicates the cardbus initiator's ability to complete the current data phase of the transaction. a data phase is completed on a rising edge of cclk when both cirdy and ctrdy are asserted. until cirdy and ctrdy are both sampled asserted, wait states are inserted. cperr 108 n14 43 p1 i/o cardbus parity error. cperr reports parity errors during cardbus transactions, except during special cycles. it is driven low by a target two clocks following that data when a parity error is detected. creq 127 l14 61 r7 i cardbus request. creq indicates to the arbiter that the cardbus pc card desires use of the cardbus bus as an initiator. cserr 136 j14 70 w8 i cardbus system error. cserr reports address parity errors and other system errors that could lead to catastrophic results. cserr is driven by the card synchronous to cclk, but deasserted by a weak pullup, and may take several cclk periods. the PCI1420 can report cserr to the system by assertion of serr on the pci interface. cstop 109 r18 45 n5 i/o cardbus stop. cstop is driven by a cardbus target to request the initiator to stop the current cardbus transaction. cstop is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. cstschg 138 h19 72 v9 i cardbus status change. cstschg alerts the system to a change in the card's status, and is used as a wake-up mechanism. ctrdy 114 p19 49 r2 i/o cardbus target ready. ctrdy indicates the cardbus target's ability to complete the current data phase of the transaction. a data phase is completed on a rising edge of cclk, when both cirdy and ctrdy are asserted; until this time, wait states are inserted. cvs1 134 j18 68 u8 i/o cardbus voltage sense 1 and cardbus voltage sense 2. cvs1 and cvs2 are used in conjunction with ccd1 and ccd2 to identify card insertion and interrogate cards cvs2 122 m19 56 p7 i/o i n con j unc ti on w ith ccd1 an d ccd2 t o id en tif y car d i nser ti on an d i n t erroga t e car d s to determine the operating voltage and card type. 2 terminal name for slot a is preceded with a_. for example, the full name for terminals 137 and j15 are a_caudio. 3 terminal name for slot b is preceded with b_. for example, the full name for terminals 71 and w9 are b_caudio.
31 3 feature/protocol descriptions the following sections give an overview of the PCI1420. figure 31 shows a simplified block diagram of the PCI1420. the pci interface includes all address/data and control signals for pci protocol. the interrupt interface includes terminals for parallel pci, parallel isa, and serialized pci and isa signaling. miscellaneous system interface terminals include multifunction terminals: suspend , ri_out /pme (power management control signal), and spkrout. pci bus PCI1420 activity led's pci950 irqser deserializer irqser 3 interrupt controller inta intb irq215 pci930 zv switch 23 23 pc card socket a tps2206 power switch 3 pc card socket b external zv port vga controller audio subsystem zoomed video 19 4 zoomed video note: the pc card interface is 68 pins for cardbus and 16-bit pc cards. in zoomed video mode 23 pins are used for routing the zo omed video signals to the vga controller. 68 68 figure 31. PCI1420 simplified block diagram 3.1 power supply sequencing the PCI1420 contains 3.3-v i/o buffers with 5-v tolerance requiring a core power supply and clamp voltages. the core power supply is always 3.3 v. the clamp voltages can be either 3.3 v or 5 v, depending on the interface. the following power-up and power-down sequences are recommended. the power-up sequence is: 1. apply 3.3-v power to the core. 2. assert grst to the device to disable the outputs during power-up. output drivers must be powered up in the high-impedance state to prevent high current levels through the clamp diodes to the 5-v supply. 3. apply the clamp voltage. the power-down sequence is: 1. use grst to switch outputs to a high-impedance state. 2. remove the clamp voltage. 3. remove the 3.3-v power from the core.
32 3.2 i/o characteristics figure 32 shows a 3-state bidirectional buffer. section 8.2, recommended operating conditions , provides the electrical characteristics of the inputs and outputs. note: the PCI1420 meets the ac specifications of the 1997 pc card standard and pci local bus specification. tied for open drain oe pad v ccp figure 32. 3-state bidirectional buffer note: unused pins (input or i/o) must be held high or low to prevent them from floating. 3.3 clamping voltages the clamping voltages are set to match whatever external environment the PCI1420 will be interfaced with: 3.3 v or 5 v. the i/o sites can be pulled through a clamping diode to a voltage rail that protects the core from external signals. the core power supply is always 3.3 v and is independent of the clamping voltages. for example, pci signaling can be either 3.3 v or 5 v, and the PCI1420 must reliably accommodate both voltage levels. this is accomplished by using a 3.3-v i/o buffer that is 5-v tolerant, with the applicable clamping voltage applied. if a system designer desires a 5-v pci bus, then v ccp can be connected to a 5-v power supply. the PCI1420 requires four separate clamping voltages because it supports a wide range of features. the four voltages are listed and defined in section 8.2, recommended operating conditions . 3.4 peripheral component interconnect (pci) interface the PCI1420 is fully compliant with the pci local bus specification . the PCI1420 provides all required signals for pci master or slave operation, and may operate in either a 5-v or 3.3-v signaling environment by connecting the v ccp terminals to the desired voltage level. in addition to the mandatory pci signals, the PCI1420 provides the optional interrupt signals inta and intb . 3.4.1 pci bus lock (lock ) the bus-locking protocol defined in the pci local bus specification is not highly recommended, but is provided on the PCI1420 as an additional compatibility feature. the pci lock signal can be routed to the mfunc4 terminal via the multifunction routing register. see section 4.30, multifunction routing register , for details. note that the use of lock is only supported by pci-to-cardbus bridges in the downstream direction (away from the processor). pci lock indicates an atomic operation that may require multiple transactions to complete. when lock is asserted, nonexclusive transactions can proceed to an address that is not currently locked. a grant to start a transaction on the pci bus does not guarantee control of lock ; control of lock is obtained under its own protocol. it is possible for different initiators to use the pci bus while a single master retains ownership of lock . note that the cardbus signal for this protocol is cblock to avoid confusion with the bus clock. an agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. the granularity of the lock is defined by pci to be 16 bytes, aligned. the lock protocol defined by the pci local bus specification allows a resource lock without interfering with nonexclusive real-time data transfer, such as video. the pci bus arbiter may be designed to support only complete bus locks using the lock protocol. in this scenario, the arbiter will not grant the bus to any other agent (other than the lock master) while lock is asserted. a complete
33 bus lock may have a significant impact on the performance of the video. the arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress. the PCI1420 supports all lock protocol associated with pci-to-pci bridges, as also defined for pci-to-cardbus bridges. this includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as pci-to-pci bridges. the potential deadlock can occur if a cardbus target supports delayed transactions and blocks access to the target until it completes a delayed read. this target characteristic is prohibited by the pci local bus specification , and the issue is resolved by the pci master using lock . 3.4.2 loading subsystem identification the subsystem vendor id register (see section 4.26) and subsystem id register (see section 4.27) make up a doubleword of pci configuration space located at offset 40h for functions 0 and 1. this doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. implementation of this unique identifier register is a pc 99 requirement. the PCI1420 offers two mechanisms to load a read-only value into the subsystem registers. the first mechanism relies upon the system bios providing the subsystem id value. the default access mode to the subsystem registers is read-only, but can be made read/write by setting bit 5 (subsysrw) in the system control register (see section 4.29) at pci offset 80h. once this bit is set, the bios can write a subsystem identification value into the registers at pci offset 40h. the bios must clear the subsysrw bit such that the subsystem vendor id register and subsystem id register is limited to read-only access. this approach saves the added cost of implementing the serial electrically erasable programmable rom (eeprom). in some conditions, such as in a docking environment, the subsystem vendor id register and subsystem id register must be loaded with a unique identifier via a serial eeprom. the PCI1420 loads the data from the serial eeprom after a reset of the primary bus. note that the suspend input gates the pci reset from the entire PCI1420 core, including the serial bus state machine (see section 3.8.4, suspend mode , for details on using suspend ). the PCI1420 provides a two-line serial bus host controller that can interface to a serial eeprom. see section 3.6, serial bus interface , for details on the two-wire serial bus controller and applications. 3.5 pc card applications this section describes the pc card interfaces of the PCI1420: ? card insertion/removal and recognition ? p 2 c power-switch interface ? zoomed video support ? speaker and audio applications ? led socket activity indicators ? pc card-16 dma support ? cardbus socket registers 3.5.1 pc card insertion/removal and recognition the 1997 pc card standard addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. through this interrogation, card voltage requirements and interface (16-bit versus cardbus) are determined. the scheme uses the card detect and voltage sense signals. the configuration of these four terminals identifies the card type and voltage requirements of the pc card interface. the encoding scheme is defined in the 1997 pc card standard and in table 31.
34 table 31. pc card card-detect and voltage-sense connections cd2 //ccd2 cd1 //ccd1 vs2 //cvs2 vs1 //cvs1 key interface voltage ground ground open open 5 v 16-bit pc card 5 v ground ground open ground 5 v 16-bit pc card 5 v and 3.3 v ground ground ground ground 5 v 16-bit pc card 5 v, 3.3 v, and x.x v ground ground open ground lv 16-bit pc card 3.3 v ground connect to cvs1 open connect to ccd1 lv cardbus pc card 3.3 v ground ground ground ground lv 16-bit pc card 3.3 v and x.x v connect to cvs2 ground connect to ccd2 ground lv cardbus pc card 3.3 v and x.x v connect to cvs1 ground ground connect to ccd2 lv cardbus pc card 3.3 v, x.x v, and y.y v ground ground ground open lv 16-bit pc card y.y v connect to cvs2 ground connect to ccd2 open lv cardbus pc card y.y v ground connect to cvs2 connect to ccd1 open lv cardbus pc card x.x v and y.y v connect to cvs1 ground open connect to ccd2 lv cardbus pc card y.y v ground connect to cvs1 ground connect to ccd1 reserved ground connect to cvs2 connect to ccd1 ground reserved 3.5.2 p 2 c power-switch interface (tps2206/2216) the PCI1420 provides a p 2 c (pcmcia peripheral control) interface for control of the pc card power switch. the clock, data, and latch terminals interface with the ti tps2206/2216 dual-slot pc card power interface switches to provide power switch support. figure 33 shows the terminal assignments of the tps2206, and figure 34 illustrates a typical application where the PCI1420 represents the pcmcia controller. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 v 5 v data clock latch reset 12 v avpp avcc avcc avcc gnd nc reset 3.3 v 5 v nc nc nc nc nc 12 v bvpp bvcc bvcc bvcc nc oc 3.3 v 3.3 v nc no internal connection figure 33. tps2206 terminal assignments the clock terminal on the PCI1420 can be an input or an output. the PCI1420 defaults the clock terminal as an input to control the serial interface and the internal state machine. bit 27 (p2cclk) in the system control register (see section 4.29) can be set by the platform bios to enable the PCI1420 to generate and drive the clock internally from the pci clock. when the system design implements clock as an output from the PCI1420, an external pulldown resistor is required.
35 PCI1420 (pcmcia controller) 12 v power supply v pp1 v pp2 v cc v cc pc card a tps2206 5 v 3.3 v clock v pp1 v pp2 v cc v cc pc card b 12 v 5 v 3.3 v avpp avcc avcc bvpp bvcc bvcc bvcc avcc supervisor reset reset data latch figure 34. tps2206 typical application 3.5.3 zoomed video support the PCI1420 allows for the implementation of zoomed video for pc cards. zoomed video is supported by setting bit 6 (zvenable) in the card control register (see section 4.32) on a per socket function basis. setting this bit puts pc card 16 address lines a25a4 of the pc card interface in the high-impedance state. these lines can then transfer video and audio data directly to the appropriate controller. card address lines a3a0 can still access pc card cis registers for pc card configuration. figure 35 illustrates a PCI1420 zv implementation. crt vga controller audio codec PCI1420 19 4 zoomed video port pcm audio input pci bus pc card interface video audio 19 4 pc card motherboard speakers figure 35. zoomed video implementation using PCI1420 not shown in figure 35 is the multiplexing scheme used to route either socket 0 or socket 1 zv source to the graphics controller. the PCI1420 provides zvstat, zvsel0 , and zvsel1 signals on the multifunction terminals to switch external bus drivers. figure 36 shows an implementation for switching between three zv streams using external logic.
36 zvstat zvsel0 zvsel1 PCI1420 2 0 1 figure 36. zoomed video switching application figure 36 illustrates an implementation using standard three-state bus drivers with active-low output enables. zvsel0 is an active-low output indicating that the socket 0 zv mode is enabled, and zvsel1 is an active-low output indicating that socket 1 zv is enabled. when both sockets have zv mode enabled, the PCI1420 defaults to indicating socket 0 enabled through zvsel0 ; however, bit 5 (port_sel) in the card control register (see section 4.32) allows software to select the socket zv source priority. table 32 illustrates the functionality of the zv output signals. table 32. pc card card-detect and voltage-sense connections inputs outputs portsel socket 0 enable socket 1 enable zvsel0 zvsel1 zvstat x 0 0 1 1 0 0 1 x 0 1 1 0 0 1 1 0 1 1 x 1 1 0 1 1 1 0 0 1 1 also shown in figure 36 is a third zv source that may be provided from a source such as a high-speed serial bus like ieee1394. the zvstat signal provides a mechanism to switch the third zv source. zvstat is an active-high output indicating that one of the PCI1420 sockets is enabled for zv mode. the implementation shown in figure 36 can be used if pc card zv is prioritized over other sources. 3.5.4 ultra zoomed video ultra zoomed video is an enhancement to the PCI1420's dma engine and is intended to improve the 16-bit bandwidth for mpeg i and mpeg ii decoder pc cards. this enhancement allows the PCI1420 to fetch 32 bits of data from memory versus the 11xx/12xx 16-bit fetch capability. this enhancement allows a higher sustained throughput to the 16-bit pc card because the PCI1420 prefetches an extra 16 bits (32 bits total) during each pci read transaction. if the pci bus becomes busy, then the PCI1420 has an extra 16 bits of data to perform back-to-back 16-bit transactions to the pc card before having to fetch more data. this feature is built into the dma engine and software is not required to enable this enhancement. note: the 11xx and 12xx series cardbus controllers have enough 16-bit bandwidth to support mpeg ii pc card decoders. but it was decided to improve the bandwidth even more in the 14xx series cardbus controllers.
37 3.5.5 internal ring oscillator the internal ring oscillator provides an internal clock source for the PCI1420 so that neither the pci clock nor an external clock is required in order for the PCI1420 to power down a socket or interrogate a pc card. this internal oscillator operates nominally at 16 khz and can be enabled by setting bit 27 (p2cclk) of the system control register (see section 4.29) at pci offset 80h to a 1. this function is disabled by default. 3.5.6 integrated pullup resistors the 1997 pc card standard requires pullup resistors on various terminals to support both cardbus and 16-bit card configurations. unlike the pci1220/1225 which required external pullup resistors, the PCI1420 has integrated all of these pullup resistors. signal name pin number socket a pin number socket b signal name ghk pdv ghk pdv a14/cperr n14 108 p1 43 ready/cint j17 135 v8 69 a15/cirdy m14 115 p5 50 cd1 /ccd1 v11 82 h3 16 vs1 /cvs1 j18 134 u8 68 a19/cblock p15 107 n6 42 a20/cstop r18 109 n5 45 a21/cdevsel p17 111 r1 47 a22/ctrdy p19 114 r2 49 vs2 /cvs2 m19 122 p7 56 reset/crst l18 124 w5 58 wait /cserr j14 136 w8 70 inpack /creq l14 127 r7 61 bvd2(spkr )/caudio j15 137 w9 71 bvd1(stschg )/cstschg h19 138 v9 72 cd2 /ccd2 h17 140 r9 74 3.5.7 spkrout and caudpwm usage spkrout carries the digital audio signal from the pc card to the system. when a 16-bit pc card is configured for i/o mode, the bvd2 pin becomes spkr . this terminal is also used in cardbus binary audio applications, and is referred to as caudio. spkr passes a ttl level digital audio signal to the PCI1420. the cardbus caudio signal also can pass a single-amplitude binary waveform. the binary audio signals from the two pc card sockets are xor'ed in the PCI1420 to produce spkrout. this output is enabled by bit 1 (spkrouten) in the card control register (see section 4.32). older controllers support caudio in binary or pwm mode but use the same pin (spkrout). some audio chips may not support both modes on one pin and may have a separate pin for binary and pwm. the PCI1420 implementation includes a signal for pwm, caudpwm, which can be routed to a mfunc terminal. bit 2 (aud2mux) located in the card control register is programmed on a per socket function basis to route a cardbus caudio pwm terminal to caudpwm. if both cardbus functions enable caudio pwm routing to caudpwm, then socket 0 audio takes precedence. see section 4.30, multifunction routing register , for details on configuring the mfunc terminals. figure 37 provides an illustration of a sample application using spkrout and caudpwm.
38 speaker subsystem binary_spkr system core logic PCI1420 caudpwm spkrout pwm_spkr figure 37. sample application of spkrout and caudpwm 3.5.8 led socket activity indicators the socket activity leds are provided to indicate when a pc card is being accessed. the leda1 and leda2 signals can be routed to the multifunction terminals. when configured for led outputs, these terminals output an active high signal to indicate socket activity. leda1 indicates socket 0 (card a) activity, and leda2 indicates socket 1 (card b) activity. the led_skt output indicates socket activity to either socket 0 or socket 1. see section 4.30, multifunction routing register , for details on configuring the multifunction terminals. the led signal is active high and is driven for 64-ms durations. when the led is not being driven high, it is driven to a low state. either of the two circuits shown in figure 38 can be implemented to provide led signaling and it is left for the board designer to implement the circuit that best fits the application. the led activity signals are valid when a card is inserted, powered, and not in reset. for pc card-16, the led activity signals are pulsed when ready/ireq is low. for cardbus cards, the led activity signals are pulsed if cframe , irdy , or creq are active. PCI1420 application- specific delay current limiting r 500 w led PCI1420 current limiting r 500 w led figure 38. two sample led circuits as indicated, the led signals are driven for a period of 64 ms by a counter circuit. to avoid the possibility of the leds appearing to be stuck when the pci clock is stopped, the led signaling is cut-off when the suspend signal is asserted, when the pci clock is to be stopped during the clock run protocol, or when in the d2 or d1 power state. if any additional socket activity occurs during this counter cycle, then the counter is reset and the led signal remains driven. if socket activity is frequent (at least once every 64 ms), then the led signals remain driven. 3.5.9 pc card-16 distributed dma support the PCI1420 supports a distributed dma slave engine for 16-bit pc card dma support. the distributed dma (ddma) slave register set provides the programmability necessary for the slave ddma engine. the ddma register configuration is provided in table 33.
39 two socket function dependent pci configuration header registers that are critical for ddma are the socket dma register 0 (see section 4.35) and the socket dma register 1 (see section 4.36). distributed dma is enabled through socket dma register 0 and the contents of this register configure the pc card-16 terminal (spkr , iois16 , or inpack ) which is used for the dma request signal, dreq . the base address of the ddma slave registers and the transfer size (bytes or words) are programmed through the socket dma register 1. refer to the programming model and register descriptions for details. table 33. distributed dma registers type register name dma base address offset r reserved page current address 00h w reser v ed page base address r reserved reserved current count 04h w reser v ed reser v ed base count r n/a reserved n/a status 08h w mode reser v ed request command r multichannel reserved n/a reserved 0ch w mask reser v ed master clear reser v ed the ddma registers contain control and status information consistent with the 8237 dma controller; however, the register locations are reordered and expanded in some cases. while the ddma register definitions are identical to those in the 8237 dma controller of the same name, some register bits defined in the 8237 dma controller do not apply to distributed dma in a pci environment. in such cases, the PCI1420 implements these obsolete register bits as read-only, nonfunctional bits. the reserved registers shown in table 33 are implemented as read-only and return 0s when read. write transactions to reserved registers have no effect. the ddma transfer is prefaced by several configuration steps that are specific to the pc card and must be completed after the pc card is inserted and interrogated. these steps include setting the proper dreq signal assignment, setting the data transfer width, and mapping and enabling the ddma register set. as discussed above, this is done through socket dma register 0 and socket dma register 1. the dma register set is then programmed similarly to an 8237 controller, and the PCI1420 awaits a dreq assertion from the pc card requesting a dma transfer. dma writes transfer data from the pc card-to-pci memory addresses. the PCI1420 accepts data 8 or 16 bits at a time, depending on the programmed data width, and then requests access to the pci bus by asserting its req signal. once the pci bus is granted in an idle state, the PCI1420 initiates a pci memory write command to the current memory address and transfers the data in a single data phase. after terminating the pci cycle, the PCI1420 accepts the next byte(s) from the pc card until the transfer count expires. dma reads transfer data from pci memory addresses to the pc card application. upon the assertion of dreq , the PCI1420 asserts req to acquire the pci bus. once the bus is granted in an idle state, the PCI1420 initiates a pci memory read operation to the current memory address and accepts 8 or 16 bits of data, depending on the programmed data width. after terminating the pci cycle, the data is passed onto the pc card. after terminating the pc card cycle, the PCI1420 requests access to the pci bus again until the transfer count has expired. the PCI1420 target interface acts normally during this procedure and accepts i/o reads and writes to the ddma registers. while a ddma transfer is in progress and the host resets the dma channel, the PCI1420 asserts tc and ends the pc card cycle(s). tc is indicated in the dma status register (see section 7.5). at the pc card interface, the PCI1420 supports demand mode transfers. the PCI1420 asserts dack during the transfer unless dreq is deasserted before tc. tc is mapped to the oe pc card terminal for dma write operations and is mapped to we pc card terminal for dma read operations. the dack signal is mapped to the pc card reg signal in all transfers, and the dreq terminal is routed to one of three options which is programmed through socket dma register 0.
310 3.5.10 pc card-16 pc/pci dma some chip sets provide a way for legacy i/o devices to do dma transfers on the pci bus. in the pc/pci dma protocol, the PCI1420 acts as a pci target device to certain dma related i/o addresses. the PCI1420 pcreq and pcgnt signals are provided as a point-to-point connection to a chipset supporting pc/pci dma. the pcreq and pcgnt signals may be routed to the mfunc2 and mfunc5 terminals, respectively. see section 4.30, multifunction routing register , for details on configuring the multifunction terminals. under the pc/pci protocol, a pci dma slave device (such as the PCI1420) requests a dma transfer on a particular channel using a serialized protocol on pcreq . the i/o dma bus master arbitrates for the pci bus and grants the channel through a serialized protocol on pcgnt when it is ready for the transfer. the i/o cycle and memory cycles are then presented on the pci bus, which performs the dma transfers similarly to legacy dma master devices. pc/pci dma is enabled for each pc card-16 slot by setting bit 19 (cdreqen) in the respective system control register (see section 4.29). on power up this bit is reset and the card pc/pci dma is disabled. bit 3 (cdma_en) of the system control register is a global enable for pc/pci dma, and is set at power-up and never cleared if the pc/pci dma mechanism is implemented. the desired dma channel for each pc card-16 slot must be configured through bits 1816 (cdmachan field) in the system control register. the channels are configured as indicated in table 34. table 34. pc/pci channel assignments system control register dma channel channel transfer data width bit 18 bit 17 bit16 dma channel data width 0 0 0 channel 0 8-bit dma transfers 0 0 1 channel 1 8-bit dma transfers 0 1 0 channel 2 8-bit dma transfers 0 1 1 channel 3 8-bit dma transfers 1 0 0 channel 4 not used 1 0 1 channel 5 16-bit dma transfers 1 1 0 channel 6 16-bit dma transfers 1 1 1 channel 7 16-bit dma transfers as in distributed dma, the pc card terminal mapped to dreq must be configured through socket dma register 0 (see section 4.35). the data transfer width is a function of channel number and the ddma slave registers are not used. when a dreq is received from a pc card and the channel has been granted, the PCI1420 decodes the i/o addresses listed in table 35 and performs actions dependent upon the address. table 35. i/o addresses used for pc/pci dma dma i/o address dma cycle type terminal count pci cycle type 00h normal 0 i/o read/write 04h normal tc 1 i/o read/write c0h verify 0 i/o read c4h verify tc 1 i/o read when the pc/pci dma is used as a pc card-16 dma mechanism, it may not provide the performance levels of ddma; however, the design of a pci target implementing pc/pci dma is considerably less complex. no bus master state machine is required to support pc/pci dma, since the dma control is centralized in the chipset. this dma scheme is often referred to as centralized dma for this reason. 3.5.11 cardbus socket registers the PCI1420 contains all registers for compatibility with the latest 1997 pc card standard . these registers exist as the cardbus socket registers and are listed in table 36.
311 table 36. cardbus socket registers register name offset socket event 00h socket mask 04h socket present state 08h socket force event 0ch socket control 10h reserved 14h reserved 18h reserved 1ch socket power management 20h 3.6 serial bus interface the PCI1420 provides a serial bus interface to load subsystem identification and select register defaults through a serial eeprom and to provide a pc card power switch interface alternative to p 2 c. see section 3.5.2, p 2 c power-switch interface (tps2206/2216) , for details. the PCI1420 serial bus interface is compatible with various i 2 c and smbus components. 3.6.1 serial bus interface implementation the PCI1420 defaults to serial bus interface are disabled. to enable the serial interface, a pulldown resistor must be implemented on the latch terminal and the appropriate pullup resistor must be implemented on the sda and scl signals, that is, the mfunc1 and mfunc4 terminals. when the interface is detected, bit 3 (sbdetect) in the serial bus control and status register (see section 4.50) is set. the sbdetect bit is cleared by a write back of 1. the PCI1420 implements a two-pin serial interface with one clock signal (scl) and one data signal (sda). when a pulldown resistor is provided on the latch terminal, the scl signal is mapped to the mfunc4 terminal and the sda signal is mapped to the mfunc1 terminal. the PCI1420 drives scl at nearly 100 khz during data transfers, which is the maximum specified frequency for standard mode i 2 c. the serial eeprom must be located at address a0h. figure 39 illustrates an example application implementing the two-wire serial bus. serial eeprom PCI1420 mfunc4 mfunc1 latch scl sda v cc figure 39. serial eeprom application some serial device applications may include pc card power switches, zv source switches, card ejectors, or other devices that may enhance the user's pc card experience. the serial eeprom device and pc card power switches are discussed in the sections that follow. 3.6.2 serial bus interface protocol the scl and sda signals are bidirectional, open-drain signals and require pullup resistors as shown in figure 39. the PCI1420 supports up to 100 kb/s data transfer rate and is compatible with standard mode i 2 c using 7-bit addressing.
312 all data transfers are initiated by the serial bus master. the beginning of a data transfer is indicated by a start condition, which is signalled when the sda line transitions to low state while scl is in the high state, as illustrated in figure 310. the end of a requested data transfer is indicated by a stop condition, which is signalled by a low-to-high transition of sda while scl is in the high state, as shown in figure 310. data on sda must remain stable during the high state of the scl signal, as changes on the sda signal during the high state of scl are interpreted as control signals, that is, a start or a stop condition. sda scl start condition stop condition change of data allowed data line stable, data valid figure 310. serial bus start/stop conditions and bit transfers data is transferred serially in 8-bit bytes. the number of bytes that may be transmitted during a data transfer is unlimited, however, each byte must be completed with an acknowledge bit. an acknowledge (ack) is indicated by the receiver pulling the sda signal low so that it remains low during the high state of the scl signal. figure 311 illustrates the acknowledge protocol. scl from master 123 78 9 sda output by transmitter sda output by receiver figure 311. serial bus protocol acknowledge the PCI1420 is a serial bus master; all other devices connected to the serial bus external to the PCI1420 are slave devices. as the bus master, the PCI1420 drives the scl clock at nearly 100 khz during bus cycles and places scl in a high-impedance state (zero frequency) during idle states. typically, the PCI1420 masters byte reads and byte writes under software control. doubleword reads are performed by the serial eeprom initialization circuitry upon a pci reset and may not be generated under software control. see section 3.6.3, serial bus eeprom application , for details on how the PCI1420 automatically loads the subsystem identification and other register defaults through a serial bus eeprom. figure 312 illustrates a byte write. the PCI1420 issues a start condition and sends the 7-bit slave device address and the command bit zero. a 0 in the r/w command bit indicates that the data transfer is a write. the slave device acknowledges if it recognizes the address. if there is no acknowledgment received by the PCI1420, then an appropriate status bit is set in the serial bus control and status register (see section 4.50). the word address byte is then sent by the PCI1420 and another slave acknowledgment is expected. then the PCI1420 delivers the data byte msb first and expects a final acknowledgment before issuing the stop condition.
313 sb6 b4 b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0 aa slave address word address r/w s/p = start/stop condition a = slave acknowledgement b7 b6 b4 b5 b3 b2 b1 b0 a p data byte figure 312. serial bus protocol byte write figure 313 illustrates a byte read. the read protocol is very similar to the write protocol except the r/w command bit must be set to 1 to indicate a read-data transfer. in addition, the PCI1420 master must acknowledge reception of the read bytes from the slave transmitter. the slave transmitter drives the sda signal during read data transfers. the scl signal remains driven by the PCI1420 master. sb6 b4 b5 b3 b2 b1 b0 1 b7 b6 b5 b4 b3 b2 b1 b0 aa slave address word address r/w s/p = start/stop condition a = slave acknowledgement b7 b6 b4 b5 b3 b2 b1 b0 m p data byte figure 313. serial bus protocol byte read figure 314 illustrates eeprom interface doubleword data collection protocol. s1 1 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 aa slave address word address r/w data byte 2 data byte 1 data byte 0 m p m m m = master acknowledgement s/p = start/stop condition a = slave acknowledgement data byte 3 m s1 1 0 00001a restart r/w slave address start figure 314. eeprom interface doubleword data collection 3.6.3 serial bus eeprom application when the pci bus is reset and the serial bus interface is detected, the PCI1420 attempts to read the subsystem identification and other register defaults from a serial eeprom. the registers and corresponding bits that may be loaded with defaults through the eeprom are provided in table 37. table 37. registers and bits loadable through serial eeprom offset reference pci offset register bits loaded from eeprom 01h 40h subsystem id 310 02h 80h system control 3129, 27, 26, 24, 15, 14, 63, 1 03h 8ch multifunction routing 270 04h 90h retry status, card control, device control, diagnostic 31, 2824, 22, 1916, 15, 13, 7, 6 figure 315 details the eeprom data format. this format must be followed for the PCI1420 to properly load initializations from a serial eeprom. any undefined condition results in a terminated load and sets the rom_err bit in the serial bus control and status register (see section 4.50).
314 slave address = 1010 000 reference(0) word address 00h byte 3 (0) word address 01h byte 2 (0) word address 02h byte 1 (0) word address 03h byte 0 (0) word address 04h rsvd rsvd rsvd reference(1) word address 08h reference(n) word address 8 (n1) byte 3 (n) word address 8 (n1) + 1 byte 2 (n) word address 8 (n1) + 2 byte 1 (n) word address 8 (n1) + 3 byte 0 (n) word address 8 (n1) + 4 rsvd rsvd rsvd eol word address 8 (n) figure 315. eeprom data format the byte at the eeprom word address 00h must either contain a valid offset reference, as listed in table 37, or an end-of-list (eol) indicator. the eol indicator is a byte value of ffh, and indicates the end of the data to load from the eeprom. only doubleword registers are loaded from the eeprom, and all bit fields must be considered when programming the eeprom. the serial eeprom is addressed at slave address 1010000b by the PCI1420. all hardware address bits for the eeprom should be tied to the appropriate level to achieve this address. the serial eeprom chip in the sample application circuit (figure 39) assumes the 1010b high address nibble. the lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to gnd. when a valid offset reference is read, four bytes are read from the eeprom, msb first, as illustrated in figure 314. the address autoincrements after every byte transfer according to the doubleword read protocol. note that the word addresses align with the data format illustrated in figure 315. the PCI1420 continues to load data from the serial eeprom until an end-of-list indicator is read. three reserved bytes are stuffed to maintain eight-byte data structures. note, the eight-byte data structure is important to provide correct addressing per the doubleword read format shown in figure 314. in addition, the reference offsets must be loaded in the eeprom in sequential order, that is 01h, 02h, 03h, 04h. if the offsets are not sequential, then the registers may be loaded incorrectly. 3.6.4 serial bus power switch application the PCI1420 does not automatically control a serial bus power switch transparently to host software as it does for p 2 c power switches. but, the PCI1420 serial bus interface can be used in conjunction with the power status, gpe , output, and support software to control a serial bus power switch. if a serial bus power switch interface is implemented, then a pulldown resistor must be provided on the PCI1420 clock terminal to reduce power consumption. the PCI1420 supports two common smbus data write protocols, write byte and send byte formats. the write byte protocol using a word address of 00h is discussed in section 3.6.2, serial bus interface protocol . the send byte protocol is shown in figure 316 using a slave address 101001x. bit 7 (prot_sel) in the serial bus control and status register, see table 425, allows the serial bus interface to operate with the send byte protocol. for more information on programming the serial bus interface, see section 3.6.5, accessing serial bus devices through software .
315 s1 1 0 0 0 1 x 0 b7 b6 b5 b4 b3 b2 b1 b0 aa slave address command code r/w s/p = start/stop condition a = slave acknowledgement p figure 316. send byte protocol the power switch may support an interrupt mode to indicate over current or other power switch related events. the PCI1420 does not implement logic to respond to these events, but does implement a flexible general-purpose interface to control these events through acpi and other handlers. see the advanced configuration and power interface (acpi) specification for details on implementing the PCI1420 in an acpi system. 3.6.5 accessing serial bus devices through software the PCI1420 provides a programming mechanism to control serial bus devices through software. the programming is accomplished through a doubleword of pci configuration space at offset b0h. table 38 lists the registers used to program a serial bus device through software. table 38. PCI1420 registers used to program serial bus devices pci offset register name description b0h serial bus data contains the data byte to send on write commands or the received data byte on read commands. b1h serial bus index the content of this register is sent as the word address on byte writes or reads. this register is not used in the quick command protocol. b2h serial bus slave address write transactions to this register initiate a serial bus transaction. the slave device address and the r/w command selector are programmed through this register. b3h serial bus control and status read data valid, general busy, and general error status are communicated through this register. in addition, the protocol select bit is programmed through this register. 3.7 programmable interrupt subsystem interrupts provide a way for i/o devices to let the microprocessor know that they require servicing. the dynamic nature of pc cards and the abundance of pc card i/o applications require substantial interrupt support from the PCI1420. the PCI1420 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. the different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards. the exca register set provides interrupt control for some 16-bit pc card functions, and the cardbus socket register set provides interrupt control for the cardbus pc card functions. the PCI1420 is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required. the PCI1420 detects pc card interrupts and events at the pc card interface and notifies the host controller using one of several interrupt signaling protocols. to simplify the discussion of interrupts in the PCI1420, pc card interrupts are classified as either card status change (csc) or as functional interrupts. the method by which any type of PCI1420 interrupt is communicated to the host interrupt controller varies from system to system. the PCI1420 offers system designers the choice of using parallel pci interrupt signaling, parallel isa-type irq interrupt signaling, or the irqser serialized isa and/or pci interrupt protocol. it is possible to use the parallel pci interrupts in combination with either parallel irqs or serialized irqs, as detailed in the sections that follow. all interrupt signalling is provided through the seven multifunction terminals, mfunc0mfunc6. 3.7.1 pc card functional and card status change interrupts pc card functional interrupts are defined as requests from a pc card application for interrupt service and are indicated by asserting specially-defined signals on the pc card interface. functional interrupts are generated by 16-bit i/o pc cards and by cardbus pc cards.
316 card status change (csc)-type interrupts are defined as events at the pc card interface that are detected by the PCI1420 and may warrant notification of host card and socket services software for service. csc events include both card insertion and removal from pc card sockets, as well as transitions of certain pc card signals. table 39 summarizes the sources of pc card interrupts and the type of card associated with them. csc and functional interrupt sources are dependent on the type of card inserted in the pc card socket. the three types of cards that can be inserted into any pc card socket are: ? 16-bit memory card ? 16-bit i/o card ? cardbus cards table 39. interrupt mask and flag registers card type event mask flag 16-bit battery conditions (bvd1, bvd2) exca offset 05h/45h/805h bits 1 and 0 exca offset 04h/44h/804h bits 1 and 0 memory wait states (ready) exca offset 05h/45h/805h bit 2 exca offset 04h/44h/804h bit 2 16 bit i/o change in card status (stschg ) exca offset 05h/45h/805h bit 0 exca offset 04h/44h/804h bit 0 16 - bit i/o interrupt request (ireq ) always enabled pci configuration offset 91h bit 0 all 16-bit pc cards power cycle complete exca offset 05h/45h/805h bit 3 exca offset 04h/44h/804h bit 3 change in card status (cstschg) socket mask bit 0 socket event bit 0 cardbus interrupt request (cint ) always enabled pci configuration offset 91h bit 0 cardb u s power cycle complete socket mask bit 3 socket event bit 3 card insertion or removal socket mask bits 2 and 1 socket event bits 2 and 1 functional interrupt events are valid only for 16-bit i/o and cardbus cards; that is, the functional interrupts are not valid for 16-bit memory cards. furthermore, card insertion and removal-type csc interrupts are independent of the card type.
317 table 310. pc card interrupt events and description card type event type signal description battery conditions csc bvd1(stschg )//cstschg a transition on bvd1 indicates a change in the pc card battery conditions. 16-bit memory y (bvd1, bvd2) csc bvd2(spkr )//caudio a transition on bvd2 indicates a change in the pc card battery conditions. wait states (ready) csc ready(ireq )//cint a transition on ready indicates a change in the ability of the memory pc card to accept or provide data. 16 bit i/o change in card status (stschg) csc bvd1(stschg )//cstschg the assertion of stschg indicates a status change on the pc card. 16 - bit i/o interrupt request (ireq) functional ready(ireq )//cint the assertion of ireq indicates an interrupt request from the pc card. cardbus change in card status (cstschg) csc bvd1(stschg )//cstschg the assertion of cstschg indicates a status change on the pc card. cardb u s interrupt request (cint ) functional ready(ireq )//cint the assertion of cint indicates an interrupt request from the pc card. all pc cards card insertion or removal csc cd1 //ccd1 , cd2 //ccd2 a transition on either cd1 //ccd1 or cd2 //ccd2 indicates an insertion or removal of a 16-bit or cardbus pc card. power cycle complete csc n/a an interrupt is generated when a pc card power-up cycle has completed. the naming convention for pc card signals describes the function for 16-bit memory, i/o cards, and cardbus. for example, ready(ireq )//cint includes ready for 16-bit memory cards, ireq for 16-bit i/o cards, and cint for cardbus cards. the 16-bit memory card signal name is first, with the i/o card signal name second, enclosed in parentheses. the cardbus signal name follows after a forward double slash (//). the 1997 pc card standard describes the power-up sequence that must be followed by the PCI1420 when an insertion event occurs and the host requests that the socket v cc and v pp be powered. upon completion of this power-up sequence, the PCI1420 interrupt scheme can be used to notify the host system (see table 310), denoted by the power cycle complete event. this interrupt source is considered a PCI1420 internal event because it depends on the completion of applying power to the socket rather than on a signal change at the pc card interface. 3.7.2 interrupt masks and flags host software may individually mask (or disable) most of the potential interrupt sources listed in table 310 by setting the appropriate bits in the PCI1420. by individually masking the interrupt sources listed, software can control those events that cause a PCI1420 interrupt. host software has some control over the system interrupt the PCI1420 asserts by programming the appropriate routing registers. the PCI1420 allows host software to route pc card csc and pc card functional interrupts to separate system interrupts. interrupt routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections. when an interrupt is signaled by the PCI1420, the interrupt service routine must determine which of the events listed in table 39 caused the interrupt. internal registers in the PCI1420 provide flags that report the source of an interrupt. by reading these status bits, the interrupt service routine can determine the action to be taken. table 39 details the registers and bits associated with masking and reporting potential interrupts. all interrupts can be masked except the functional pc card interrupts, and an interrupt status flag is available for all types of interrupts. notice that there is not a mask bit to stop the PCI1420 from passing pc card functional interrupts through to the appropriate interrupt scheme. these interrupts are not valid until the card is properly powered, and there should never be a card interrupt that does not require service after proper initialization. table 39 lists the various methods of clearing the interrupt flag bits. the flag bits in the exca registers (16-bit pc card-related interrupt flags) can be cleared using two different methods. one method is an explicit write of 1 to the flag bit to clear and the other is by reading the flag bit register. the selection of flag bit clearing is made by bit 2 (ifcmode) in the exca global control register (see section 5.22), located at exca offset 1eh/5eh/81eh, and defaults to the flag cleared on read method.
318 the cardbus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register (see section 6.1). although some of the functionality is shared between the cardbus registers and the exca registers, software should not program the chip through both register sets when a cardbus card is functioning. 3.7.3 using parallel irq interrupts the seven multifunction terminals, mfunc6mfunc0, implemented in the PCI1420 may be routed to obtain a subset of the isa irqs . the irq choices provide ultimate flexibility in pc card host interruptions. to use the parallel isa type irq interrupt signaling, software must program the device control register (see section 4.33), located at pci offset 92h, to select the parallel irq signaling scheme. see section 4.30, multifunction routing register , for details on configuring the multifunction terminals. a system using parallel irqs requires (at a minimum) one pci terminal, inta , to signal csc events. this requirement is dictated by certain card and socket services software. the inta requirement calls for routing the mfunc0 terminal for inta signaling. the intrtie bit is used, in this case, to route socket b interrupt events to inta . this leaves (at a maximum) six different irqs to support legacy 16-bit pc card functions. as an example, suppose the six irqs used by legacy pc card applications are irq3, irq4, irq5, irq10, irq11, and irq15. the multifunction routing register must be programmed to a value of 0x0fba5432. this value routes the mfunc0 terminal to inta signaling and routes the remaining terminals as illustrated in figure 317. not shown is that inta must also be routed to the programmable interrupt controller (pic), or to some circuitry that provides parallel pci interrupts to the host. PCI1420 pic mfunc1 mfunc2 mfunc3 mfunc4 mfunc5 mfunc6 irq3 irq4 irq5 irq10 irq11 irq15 figure 317. irq implementation power-on software is responsible for programming the multifunction routing register to reflect the irq configuration of a system implementing the PCI1420. the multifunction routing register is shared between the two PCI1420 functions, and only one write to function 0 or 1 is necessary to configure the mfunc6mfunc0 signals. writing to only function 0 is recommended. see section 4.30, multifunction routing register , for details on configuring the multifunction terminals. the parallel isa type irq signaling from the mfunc6mfunc0 terminals is compatible with those input directly into the 8259 pic. the parallel irq option is provided for system designs that require legacy isa irqs. design constraints may demand more mfunc6mfunc0 irq terminals than the PCI1420 makes available. 3.7.4 using parallel pci interrupts parallel pci interrupts are available when exclusively in parallel pci interrupt mode parallel isa irq signaling mode, and when only irqs are serialized with the irqser protocol. both inta and intb can be routed to mfunc terminals (mfunc0 and mfunc1). however, both socket functions' interrupts can be routed to inta (mfunc0) if bit 29 (intrtie) is set in the system control register (see section 4.29). the intrtie bit affects the read-only value provided through accesses to the interrupt pin register (see section 4.24). when intrtie bit is set, both functions return a value of 0x01 on reads from the interrupt pin register for both parallel and serial pci interrupts. table 311 summarizes the interrupt signalling modes.
319 table 311. interrupt pin register cross reference interrupt signaling mode intrtie bit intpin function 0 intpin function 1 parallel pci interrupts only 0 0x01 (inta ) 0x02 (intb ) parallel irq and parallel pci interrupts 0 0x01 (inta ) 0x02 (intb ) irq serialized (irqser) and parallel pci interrupts 0 0x01 (inta ) 0x02 (intb ) irq and pci serialized (irqser) interrupts (default) 0 0x01 (inta ) 0x02 (intb ) parallel pci interrupts only 1 0x01 (inta ) 0x01 (inta ) parallel irq and parallel pci interrupts 1 0x01 (inta ) 0x01 (inta ) irq serialized (irqser) and parallel pci interrupts 1 0x01 (inta ) 0x01 (inta ) irq and pci serialized (irqser) interrupts 1 0x01 (inta ) 0x01 (inta ) 3.7.5 using serialized irqser interrupts the serialized interrupt protocol implemented in the PCI1420 uses a single terminal to communicate all interrupt status information to the host controller. the protocol defines a serial packet consisting of a start cycle, multiple interrupt indication cycles, and a stop cycle. all data in the packet is synchronous with the pci clock. the packet data describes 16 parallel isa irq signals and the optional 4 pci interrupts inta , intb , intc , and intd . for details on the irqser protocol refer to the document serialized irq support for pci systems . 3.7.6 smi support in the PCI1420 the PCI1420 provides a mechanism for interrupting the system when power changes have been made to the pc card socket interfaces. the interrupt mechanism is designed to fit into a system maintenance interrupt (smi) scheme. smi interrupts are generated by the PCI1420, when enabled, after a write cycle to either the socket control register (see section 6.5) of the cardbus register set or the exca power control register (see section 5.3) causes a power cycle change sequence sent on the power switch interface. the smi control is programmed through three bits in the system control register (see section 4.29). these bits are smiroute (bit 26), smistatus (bit 25), and smienb (bit 24). table 312 describes the smi control bits function. table 312. smi control bit name function smiroute this shared bit controls whether the smi interrupts are sent as a csc interrupt or as irq2. smistat this socket dependent bit is set when an smi interrupt is pending. this status flag is cleared by writing back a 1. smienb when set, smi interrupt generation is enabled. this bit is shared by functions 0 and 1. if csc smi interrupts are selected, then the smi interrupt is sent as the csc on a per socket basis. the csc interrupt can be either level or edge mode, depending upon the cscmode bit in the exca global control register (see section 5.22). if irq2 is selected by smiroute, then the irqser signaling protocol supports smi signaling in the irq2 irq/data slot. in a parallel isa irq system, the support for an active low irq2 is provided only if irq2 is routed to either mfunc3 or mfunc6 through the multifunction routing register (see section 4.30). 3.8 power management overview in addition to the low-power cmos technology process used for the PCI1420, various features are designed into the device to allow implementation of popular power-saving techniques. these features and techniques are discussed in this section.
320 3.8.1 clock run protocol the pci clkrun feature is the primary method of power management on the pci interface of the PCI1420. clkrun signalling is provided through the mfunc6 terminal. since some chip sets do not implement clkrun , this is not always available to the system designer, and alternate power savings features are provided. for details on the clkrun protocol see the pci mobile design guide . the PCI1420 does not permit the central resource to stop the pci clock under any of the following conditions: ? bit 1 (keepclk) in the system control register (see section 4.29) is set. ? the pc card-16 resource manager is busy. ? the PCI1420 cardbus master state machine is busy. a cycle may be in progress on cardbus. ? the PCI1420 master is busy. there may be posted data from cardbus to pci in the PCI1420. ? interrupts are pending. ? the cardbus cclk for either socket has not been stopped by the PCI1420 cclkrun manager. the PCI1420 restarts the pci clock using the clkrun protocol under any of the following conditions: ? a pc card-16 ireq or a cardbus cint has been asserted by either card. ? a cardbus cbwake (cstschg) or pc card-16 stschg /ri event occurs in either socket. ? a cardbus attempts to start the cclk using cclkrun . ? a cardbus card arbitrates for the cardbus bus using creq . ? a 16-bit dma pc card asserts dreq . 3.8.2 cardbus pc card power management the PCI1420 implements its own card power management engine that can turn off the cclk to a socket when there is no activity to the cardbus pc card. the pci clock-run protocol is followed on the cardbus cclkrun interface to control this clock management. 3.8.3 16-bit pc card power management the coe (bit 7, exca power control register) and pwrdwn (bit 0, exca global control register) bits are provided for 16-bit pc card power management. the coe bit places the card interface in a high-impedance state to save power. the power savings when using this feature are minimal. the coe bit will reset the pc card when used, and the pwrdwn bit will not. furthermore, the pwrdwn bit is an automatic coe, that is, the pwrdwn performs the coe function when there is no card activity. note: the 16-bit pc card must implement the proper pullup resistors for the coe and pwrdwn modes. 3.8.4 suspend mode the suspend signal, provided for backward compatibility, gates the prst (pci reset) signal and the grst (global reset) signal from the PCI1420. besides gating prst and grst , suspend also gates pclk inside the PCI1420 in order to minimize power consumption. gating pclk does not create any issues with respect to the power switch interface in the PCI1420. this is because the PCI1420 does not depend on the pci clock to clock the power switch interface. there are two methods to clock the power switch interface in the PCI1420: ? use an external clock to the PCI1420 clock pin ? use the internal oscillator
321 it should also be noted that asynchronous signals, such as card status change interrupts and ri_out , can be passed to the host system without a pci clock. however, if card status change interrupts are routed over the serial interrupt stream, then the pci clock will have to be restarted in order to pass the interrupt, because neither the internal oscillator nor an external clock is routed to the serial interrupt state machine. figure 318 is a functional implementation diagram. PCI1420 core reset suspend gnt pclk pclkin resetin suspendin figure 318. suspend functional implementation figure 319 is a signal diagram of the suspend function. reset gnt suspend pclk resetin suspendin pclkin external terminals internal signals figure 319. signal diagram of suspend function 3.8.5 requirements for suspend mode the suspend mode prevents the clearing of all register contents on the assertion of reset (prst or grst ) which would require the reconfiguration of the PCI1420 by software. asserting the suspend signal places the controller's pci outputs in a high impedance state and gates the pclk signal internally to the controller unless a pci transaction is currently in process (gnt is asserted). it is important that the pci bus not be parked on the PCI1420 when suspend is asserted because the outputs are in a high impedance state. the gpios, mfunc signals, and ri_out signals are all active during suspend , unless they are disabled in the appropriate PCI1420 registers.
322 3.8.6 ring indicate the ri_out output is an important feature in power management, allowing a system to go into a suspended mode and wake up on modem rings and other card events. ti designed flexibility permits this signal to fit wide platform requirements. ri_out on the PCI1420 can be asserted under any of the following conditions: ? a 16-bit pc card modem in a powered socket asserts ri to indicate to the system the presence of an incoming call. ? a powered down cardbus card asserts cstschg (cbwake) requesting system and interface wake up. ? a powered cardbus card asserts cstschg from the insertion/removal of cards or change in battery voltage levels. figure 320 shows various enable bits for the PCI1420 ri_out function; however, it does not show the masking of csc events. see table 39 for a detailed description of csc interrupt masks and flags. card i/f pc card socket 0 csc cstsmask rienb ri_out ri_out function ringen cdresume csc ri card i/f pc card socket 1 csc cstsmask ringen cdresume csc ri figure 320. ri_out functional diagram ri from the 16-bit pc card interface is masked by bit 7 (ringen) in the exca interrupt and general control register (see section 5.4). this is programmed on a per-socket basis and is only applicable when a 16-bit card is powered in the socket. the cbwake signaling to ri_out is enabled through the same mask as the csc event for cstschg. the mask bit (bit 0, cstsmask) is programmed through the socket mask register (see section 6.2) in the cardbus socket registers. 3.8.7 pci power management the pci bus power management interface specification for pci to cardbus bridges establishes the infrastructure required to let the operating system control the power of pci functions. this is done by defining a standard pci interface and operations to manage the power of pci functions on the bus. the pci bus and the pci functions can be assigned one of four software-visible power management states that result in varying levels of power savings.
323 the four power management states of pci functions are: ? d0 fully-on state ? d1 and d2 intermediate states ? d3 off state similarly, bus power states of the pci bus are b0b3. the bus power states b0b3 are derived from the device power state of the originating bridge device. for the operating system (os) to power manage the device power states on the pci bus, the pci function should support four power management operations. these operations are: ? capabilities reporting ? power status reporting ? setting the power state ? system wake up the os identifies the capabilities of the pci function by traversing the new capabilities list. the presence of capabilities in addition to the standard pci capabilities is indicated by a 1 in bit 4 (caplist) of the status register (see section 4.5). the capabilities pointer provides access to the first item in the linked list of capabilities. for the PCI1420, a cardbus bridge with pci configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. the first byte of each capability register block is required to be a unique id of that capability. pci power management has been assigned an id of 01h. the next byte is a pointer to the next pointer item in the list of capabilities. if there are no more items in the list, then the next item pointer should be set to 0. the registers following the next item pointer are specific to the function's capability. the pci power management capability implements the register block outlined in table 313. table 313. power management registers register name offset power management capabilities next item pointer capability id a0h data pmcsr bridge support extensions power management control status (csr) a4h the power management capabilities register (see section 4.39) is a static read-only register that provides information on the capabilities of the function related to power management. the pmcsr register (see section 4.40) enables control of power management states and enables/monitors power management events. the data register is an optional register that can provide dynamic data. for more information on pci power management, see the pci bus power management interface specification for pci to cardbus bridges . 3.8.8 cardbus bridge power management the pci bus power management interface specification for pci to cardbus bridges was approved by pcmcia in december of 1997. this specification follows the device and bus state definitions provided in the pci bus power management interface specification published by the pci special interest group (sig). the main issue addressed in the pci bus power management interface specification for pci to cardbus bridges is wake-up from d3 hot or d3 cold without losing wake-up context (also called pme context). the specific issues addressed by the pci bus power management interface specification for pci to cardbus bridges for d3 wake up are as follows: ? preservation of device context: the specification states that a reset must occur when transitioning from d3 to d0. some method to preserve wake-up context must be implemented so that the reset does not clear the pme context registers. ? power source in d3 cold if wake-up support is required from this state.
324 the texas instruments PCI1420 addresses these d3 wake-up issues in the following manner: ? two resets are provided to handle preservation of pme context bits: global reset (grst ) is used only on the initial boot up of the system after power up. it places the PCI1420 in its default state and requires bios to configure the device before becoming fully functional. pci reset (prst ) now has dual functionality based on whether pme is enabled or not. if pme is enabled, then pme context is preserved. if pme is not enabled, then prst acts the same as a normal pci reset. please see the master list of pme context bits in section 3.8.10. ? power source in d3 cold if wake-up support is required from this state. since v cc is removed in d3 cold , an auxiliary power source must be supplied to the PCI1420 v cc pins. consult the pci14xx implemenation guide for d3 wake-up or the pci power management interface specification for pci to cardbus bridges for further information. 3.8.9 acpi support the advanced configuration and power interface (acpi) specification provides a mechanism that allows unique pieces of hardware to be described to the acpi driver. the PCI1420 offers a generic interface that is compliant with acpi design rules. two doublewords of general-purpose acpi programming bits reside in PCI1420 pci configuration space at offset a8h. the programming model is broken into status and control functions. in compliance with acpi, the top level event status and enable bits reside in general-purpose event status (see section 4.43) and general-purpose event enable (see section 4.44) registers. the status and enable bits are implemented as defined by acpi and illustrated in figure 321. status bit event output event input enable bit figure 321. block diagram of a status/enable cell the status and enable bits generate an event that allows the acpi driver to call a control method associated with the pending status bit. the control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. a hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report events. for more information of acpi, see the advanced configuration and power interface (acpi) specification. 3.8.10 master list of pme context bits and global reset only bits if the pme enable bit (pci offset a4h, bit 8) is asserted, then the assertion of prst will not clear the following pme context bits. if the pme enable bit is not asserted, then the pme context bits are cleared with prst . the pme context bits are: ? bridge control register (pci offset 3eh): bit 22 ? system control register (pci offset 80h): bits 10, 9, 8 ? power management control/status register (pci offset a4h): bits 15, 8 ? exca identification and revision register (exca offset 800h): bits 30, 29, 23, 21, 20, 19, 17, 16 ? exca card status change register (exca offset 804h): bits 118, 30 ? cardbus socket event register (cardbus offset 00h): bits 30 ? cardbus socket mask register (cardbus offset 04h): bits 30 ? cardbus socket present state register (cardbus offset 08h): bits 137, 51 ? cardbus socket control register (cardbus offset 10h): bits 6, 5, 4, 2, 1, 0
325 global reset will place all registers in their default state regardless of the state of the pme enable bit. the grst signal is gated only by the suspend signal. this means that assertion of suspend blocks the grst signal internally, thus preserving all register contents. the registers cleared by grst are: ? status register (pci offset 06h): bits 1511, 8 ? secondary status register (pci offset 16h): bits 1511, 8 ? interrupt pin register (pci offset 3dh): bits 1,0 (function 1 only) ? subsystem vendor id register (pci offset 40h): bits 150 ? subsystem id register (pci offset 42h): bits 150 ? pc card 16-bit legacy mode base address register (pci offset 44h): bits 311 ? system control register (pci offset 80h): bits 3129, 2713, 11, 60 ? multifunction routing register (pci offset 8ch): bits 270 ? retry status register (pci offset 90h): bits 75, 3, 1 ? card control register (pci offset 91h): bits 75, 20 ? device control register (pci offset 92h): bits 75, 30 ? diagnostic register (pci offset 93h): bits 70 ? socket dma register 0 (pci offset 94h): bits 10 ? socket dma register 1 (pci offset 98h): bits 154, 20 ? power management capabilities register (pci offset a2h): bit 15 ? general-purpose event status register (pci offset a8h): bits 15, 14 ? general-purpose event enable register (pci offset aah): bits 15, 14, 11, 8, 40 ? general-purpose output (pci offset aeh): bits 40 ? serial bus data (pci offset b0h): bits 70 ? serial bus index (pci offset b1h): bits 70 ? serial bus slave address register (pci offset b2h): bits 70 ? serial bus control and status register (pci offset b3h): bits 7, 50 ? exca identification and revision register (exca offset 00h): bits 70 ? exca global control register (exca offset 1eh): bits 20 ? socket present state register (cardbus offset 08h): bit 29 ? socket power management (cardbus offset 20h): bits 25, 24
326
41 4 pc card controller programming model this section describes the PCI1420 pci configuration registers that make up the 256-byte pci configuration header for each PCI1420 function. as noted, some bits are global in nature and are accessed only through function 0. 4.1 pci configuration registers (functions 0 and 1) the PCI1420 is a multifunction pci device, and the pc card controller is integrated as pci functions 0 and 1. the configuration header is compliant with the pci local bus specification as a cardbus bridge header and is pc 99 compliant as well. table 41 shows the pci configuration header, which includes both the predefined portion of the configuration space and the user-definable registers. table 41. pci configuration registers (functions 0 and 1) register name offset device id vendor id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch cardbus socket/exca base address 10h secondary status reserved capability pointer 14h cardbus latency timer subordinate bus number cardbus bus number pci bus number 18h cardbus memory base register 0 1ch cardbus memory limit register 0 20h cardbus memory base register 1 24h cardbus memory limit register 1 28h cardbus i/o base register 0 2ch cardbus i/o limit register 0 30h cardbus i/o base register 1 34h cardbus i/o limit register 1 38h bridge control interrupt pin interrupt line 3ch subsystem id subsystem vendor id 40h pc card 16-bit i/f legacy-mode base address 44h reserved 48h7ch system control 80h reserved 84h88h multifunction routing 8ch diagnostic device control card control retry status 90h socket dma register 0 94h socket dma register 1 98h reserved 9ch power management capabilities next-item pointer capability id a0h pm data pmcsr bridge support extensions power management control/status a4h general-purpose event enable general-purpose event status a8h general-purpose output general-purpose input ach serial bus control/status serial bus slave address serial bus index serial bus data b0h reserved b4hfch
42 4.2 vendor id register this 16-bit register contains a value allocated by the pci sig (special interest group) and identifies the manufacturer of the pci device. the vendor id assigned to ti is 104ch. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vendor id type r r r r r r r r r r r r r r r r default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 register: vendor id type: read-only offset: 00h (functions 0, 1) default: 104ch 4.3 device id register this 16-bit register contains a value assigned to the PCI1420 by ti. the device identification for the PCI1420 is ac51h. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name device id type r r r r r r r r r r r r r r r r default 1 0 1 0 1 1 0 0 0 1 0 1 0 0 0 1 register: device id type: read-only offset: 02h (functions 0, 1) default: ac51h
43 4.4 command register the command register provides control over the PCI1420 interface to the pci bus. all bit functions adhere to the definitions in pci local bus specification . none of the bit functions in this register are shared between the two PCI1420 pci functions. two command registers exist in the PCI1420, one for each function. software must manipulate the two PCI1420 functions as separate entities when enabling functionality through the command register. the serr_en and perr_en enable bits in this register are internally wired-or between the two functions, and these control bits appear separately according to their software function. see table 42 for the complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name command type r r r r r r r r/w r r/w r/w r r r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: command type: read-only, read/write offset: 04h default: 0000h table 42. command register bit signal type function 1510 rsvd r reserved. bits 1510 return 0s when read. 9 fbb_en r fast back-to-back enable. the PCI1420 does not generate fast back-to-back transactions; therefore, bit 9 returns 0 when read. 8 serr_en r/w system error (serr ) enable. bit 8 controls the enable for the serr driver on the pci interface. serr can be asserted after detecting an address parity error on the pci bus. both bits 8 and 6 must be set for the PCI1420 to report address parity errors. 0 = disable serr output driver (default) 1 = enable serr output driver 7 step_en r address/data stepping control. the PCI1420 does not support address/data stepping; therefore, bit 7 is hardwired to 0. 6 perr_en r/w parity error response enable. bit 6 controls the PCI1420's response to parity errors through perr . data parity errors are indicated by asserting perr , whereas address parity errors are indicated by asserting serr . 0 = PCI1420 ignores detected parity error (default) 1 = PCI1420 responds to detected parity errors 5 vga_en r/w vga palette snoop. bit 5 controls how pci devices handle accesses to video graphics array (vga) palette registers. 4 mwi_en r memory write and invalidate enable. bit 4 controls whether a pci initiator device can generate memory write and invalidate commands. the PCI1420 controller does not support memory write and invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. 3 special r special cycles. bit 3 controls whether or not a pci device ignores pci special cycles. the PCI1420 does not respond to special cycle operations; therefore, this bit is hardwired to 0. 2 mast_en r/w bus master control. bit 2 controls whether or not the PCI1420 can act as a pci bus initiator (master). the PCI1420 can take control of the pci bus only when this bit is set. 0 = disables the PCI1420's ability to generate pci bus accesses (default) 1 = enables the PCI1420's ability to generate pci bus accesses 1 mem_en r/w memory space enable. bit 1 controls whether or not the PCI1420 can claim cycles in pci memory space. 0 = disables the PCI1420's response to memory space accesses (default) 1 = enables the PCI1420's response to memory space accesses 0 io_en r/w i/o space control. bit 0 controls whether or not the PCI1420 can claim cycles in pci i/o space. 0 = disables the PCI1420 from responding to i/o space accesses (default) 1 = enables the PCI1420 to respond to i/o space accesses
44 4.5 status register the status register provides device information to the host system. bits in this register may be read normally. a bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. all bit functions adhere to the definitions in the pci local bus specification . pci bus status is shown through each function. see table 43 for the complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name status type r/c r/c r/c r/c r/c r r r/c r r r r r r r r default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 register: status type: read-only, read/write to clear offset: 06h (functions 0, 1) default: 0210h table 43. status register bit signal type function 15 par_err r/c detected parity error. bit 15 is set when a parity error is detected (either address or data). 14 sys_err r/c signaled system error. bit 14 is set when serr is enabled and the PCI1420 signals a system error to the host. 13 mabort r/c received master abort. bit 13 is set when a cycle initiated by the PCI1420 on the pci bus has been terminated by a master abort. 12 tabt_rec r/c received target abort. bit 12 is set when a cycle initiated by the PCI1420 on the pci bus was terminated by a target abort. 11 tabt_sig r/c signaled target abort. bit 11 is set by the PCI1420 when it terminates a transaction on the pci bus with a target abort. 109 pci_speed r devsel timing. these bits encode the timing of devsel and are hardwired 01b, indicating that the PCI1420 asserts pci_speed at a medium speed on nonconfiguration cycle accesses. 8 datapar r/c data parity error detected. 0 = the conditions for setting bit 8 have not been met. 1 = a data parity error occurred, and the following conditions were met: a. perr was asserted by any pci device including the PCI1420. b. the PCI1420 was the bus master during the data parity error. c. the parity error response bit is set in the command. 7 fbb_cap r fast back-to-back capable. the PCI1420 cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. 6 udf r user-definable feature support. the PCI1420 does not support the user-definable features; therefore, bit 6 is hardwired to 0. 5 66mhz r 66-mhz capable. the PCI1420 operates at a maximum pclk frequency of 33 mhz; therefore, bit 5 is hardwired to 0. 4 caplist r capabilities list. bit 4 returns 1 when read. this bit indicates that capabilities in addition to standard pci capabilities are implemented. the linked list of pci power management capabilities is implemented in this function. 30 rsvd r reserved. bits 30 return 0s when read.
45 4.6 revision id register the revision id register indicates the silicon revision of the PCI1420. bit 7 6 5 4 3 2 1 0 name revision id type r r r r r r r r default 0 0 0 0 0 0 0 1 register: revision id type: read-only offset: 08h (functions 0, 1) default: 01h 4.7 pci class code register the class code register recognizes the PCI1420 functions 0 and 1 as a bridge device (06h) and cardbus bridge device (07h) with a 00h programming interface. bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pci class code base class subclass programming interface type r r r r r r r r r r r r r r r r r r r r r r r r default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 register: pci class code type: read-only offset: 09h (functions 0, 1) default: 060700h 4.8 cache line size register the cache line size register is programmed by host software to indicate the system cache line size. bit 7 6 5 4 3 2 1 0 name cache line size type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: cache line size type: read/write offset: 0ch (functions 0, 1) default: 00h
46 4.9 latency timer register the latency timer register specifies the latency timer for the PCI1420 in units of pci clock cycles. when the PCI1420 is a pci bus initiator and asserts frame , the latency timer begins counting from zero. if the latency timer expires before the PCI1420 transaction has terminated, then the PCI1420 terminates the transaction when its gnt is deasserted. this register is separate for each of the two PCI1420 functions. this allows platforms to prioritize the two PCI1420 functions' use of the pci bus. bit 7 6 5 4 3 2 1 0 name latency timer type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: latency timer type: read/write offset: 0dh default: 00h 4.10 header type register this register returns 82h when read, indicating that the PCI1420 functions 0 and 1 configuration spaces adhere to the cardbus bridge pci header. the cardbus bridge pci header ranges from pci register 0 to 7fh, and 80hffh is user-definable extension registers. bit 7 6 5 4 3 2 1 0 name header type type r r r r r r r r default 1 0 0 0 0 0 1 0 register: header type type: read-only offset: 0eh (functions 0, 1) default: 82h 4.11 bist register because the PCI1420 does not support a built-in self-test (bist), this register returns the value of 00h when read. bit 7 6 5 4 3 2 1 0 name bist type r r r r r r r r default 0 0 0 0 0 0 0 0 register: bist type: read-only offset: 0fh (functions 0, 1) default: 00h
47 4.12 cardbus socket/exca base-address register the cardbus socket/exca base-address register is programmed with a base address referencing the cardbus socket registers and the memory-mapped exca register set. bits 3112 are read/write and allow the base address to be located anywhere in the 32-bit pci memory address space on a 4-kbyte boundary. bits 110 are read-only, returning 0s when read. when software writes all 1s to this register, the value read back is ffff f000h, indicating that at least 4k bytes of memory address space are required. the cardbus registers start at offset 000h, and the memory-mapped exca registers begin at offset 800h. since this register is not shared by functions 0 and 1, mapping of each socket control is performed separately. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cardbus socket/exca base-address type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cardbus socket/exca base-address type r/w r/w r/w r/w r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: cardbus socket/exca base-address type: read-only, read/write offset: 10h default: 0000 0000h 4.13 capability pointer register the capability pointer register provides a pointer into the pci configuration header where the pci power management register block resides. pci header doublewords at a0h and a4h provide the power management (pm) registers. each socket has its own capability pointer register. this register returns a0h when read. bit 7 6 5 4 3 2 1 0 name capability pointer type r r r r r r r r default 1 0 1 0 0 0 0 0 register: capability pointer type: read-only offset: 14h default: a0h
48 4.14 secondary status register the secondary status register is compatible with the pci-to-pci bridge secondary status register and indicates cardbus-related device information to the host system. this register is very similar to the pci status register (offset 06h); status bits are cleared by writing a 1. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name secondary status type r/c r/c r/c r/c r/c r r r/c r r r r r r r r default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 register: secondary status type: read-only, read/write to clear offset: 16h default: 0200h table 44. secondary status register bit signal type function 15 cbparity r/c detected parity error. bit 15 is set when a cardbus parity error is detected (either address or data). 14 cbserr r/c signaled system error. bit 14 is set when cserr is signaled by a cardbus card. the PCI1420 does not assert cserr . 13 cbmabort r/c received master abort. bit 13 is set when a cycle initiated by the PCI1420 on the cardbus bus has been terminated by a master abort. 12 rec_cbta r/c received target abort. bit 12 is set when a cycle initiated by the PCI1420 on the cardbus bus is terminated by a target abort. 11 sig_cbta r/c signaled target abort. bit 11 is set by the PCI1420 when it terminates a transaction on the cardbus bus with a target abort. 109 cb_speed r cdevsel timing. these bits encode the timing of cdevsel and are hardwired 01b, indicating that the PCI1420 asserts cb_speed at a medium speed. 8 cb_dpar r/c cardbus data parity error detected. 0 = the conditions for setting bit 8 have not been met. 1 = a data parity error occurred and the following conditions were met: a. cperr was asserted on the cardbus interface. b. the PCI1420 was the bus master during the data parity error. c. the parity error response bit is set in the bridge control. 7 cbfbb_cap r fast back-to-back capable. the PCI1420 cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. 6 cb_udf r user-definable feature support. the PCI1420 does not support the user-definable features; therefore, bit 6 is hardwired to 0. 5 cb66mhz r 66-mhz capable. the PCI1420 cardbus interface operates at a maximum cclk frequency of 33 mhz; therefore, bit 5 is hardwired to 0. 40 rsvd r reserved. bits 40 return 0s when read.
49 4.15 pci bus number register this register is programmed by the host system to indicate the bus number of the pci bus to which the PCI1420 is connected. the PCI1420 uses this register in conjunction with the cardbus bus number and subordinate bus number registers to determine when to forward pci configuration cycles to its secondary buses. bit 7 6 5 4 3 2 1 0 name pci bus number type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: pci bus number type: read/write offset: 18h (functions 0, 1) default: 00h 4.16 cardbus bus number register this register is programmed by the host system to indicate the bus number of the cardbus bus to which the PCI1420 is connected. the PCI1420 uses this register in conjunction with the pci bus number and subordinate bus number registers to determine when to forward pci configuration cycles to its secondary buses. this register is separate for each PCI1420 controller function. bit 7 6 5 4 3 2 1 0 name cardbus bus number type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: cardbus bus number type: read/write offset: 19h default: 00h 4.17 subordinate bus number register this register is programmed by the host system to indicate the highest-numbered bus below the cardbus bus. the PCI1420 uses this register in conjunction with the pci bus number and cardbus bus number registers to determine when to forward pci configuration cycles to its secondary buses. this register is separate for each cardbus controller function. bit 7 6 5 4 3 2 1 0 name subordinate bus number type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: subordinate bus number type: read/write offset: 1ah default: 00h
410 4.18 cardbus latency timer register this register is programmed by the host system to specify the latency timer for the PCI1420 cardbus interface in units of cclk cycles. when the PCI1420 is a cardbus initiator and asserts cframe , the cardbus latency timer begins counting. if the latency timer expires before the PCI1420 transaction has terminated, then the PCI1420 terminates the transaction at the end of the next data phase. a recommended minimum value for this register is 40h, which allows most transactions to be completed. bit 7 6 5 4 3 2 1 0 name cardbus latency timer type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: cardbus latency timer type: read/write offset: 1bh (functions 0, 1) default: 00h 4.19 memory base registers 0, 1 the memory base registers indicate the lower address of a pci memory address range. these registers are used by the PCI1420 to determine when to forward a memory transaction to the cardbus bus and when to forward a cardbus cycle to pci. bits 3112 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit pci memory space on 4-kbyte boundaries. bits 110 are read-only and always return 0s. write transactions to these bits have no effect. bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. the memory base register or the memory limit register must be nonzero for the PCI1420 to claim any memory transactions through cardbus memory windows (that is, these windows are not enabled by default to pass the first 4k bytes of memory to cardbus). bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name memory base registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name memory base registers 0, 1 type r/w r/w r/w r/w r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: memory base registers 0, 1 type: read-only, read/write offset: 1ch, 24h default: 0000 0000h
411 4.20 memory limit registers 0, 1 the memory limit registers indicate the upper address of a pci memory address range. these registers are used by the PCI1420 to determine when to forward a memory transaction to the cardbus bus and when to forward a cardbus cycle to pci. bits 3112 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit pci memory space on 4-kbyte boundaries. bits 110 are read-only and always return 0s. write transactions to these bits have no effect. bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. the memory base register or the memory limit register must be nonzero for the PCI1420 to claim any memory transactions through cardbus memory windows (that is, these windows are not enabled by default to pass the first 4k bytes of memory to cardbus). bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name memory limit registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name memory limit registers 0, 1 type r/w r/w r/w r/w r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: memory limit registers 0, 1 type: read-only, read/write offset: 20h, 28h default: 0000 0000h 4.21 i/o base registers 0, 1 the i/o base registers indicate the lower address of a pci i/o address range. these registers are used by the PCI1420 to determine when to forward an i/o transaction to the cardbus bus and when to forward a cardbus cycle to the pci bus. the lower 16 bits of this register locate the bottom of the i/o window within a 64-kbyte page, and the upper 16 bits (3116) are a page register which locates this 64-kbyte page in 32-bit pci i/o address space. bits 312 are read/write. bits 1 and 0 are read-only and always return 0s, forcing i/o windows to be aligned on a natural doubleword boundary. note: either the i/o base or the i/o limit register must be nonzero to enable any i/o transactions. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name i/o base registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name i/o base registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: i/o base registers 0, 1 type: read-only, read/write offset: 2ch, 34h default: 0000 0000h
412 4.22 i/o limit registers 0, 1 the i/o limit registers indicate the upper address of a pci i/o address range. these registers are used by the PCI1420 to determine when to forward an i/o transaction to the cardbus bus and when to forward a cardbus cycle to pci. the lower 16 bits of this register locate the top of the i/o window within a 64-kbyte page, and the upper 16 bits are a page register that locates this 64-kbyte page in 32-bit pci i/o address space. bits 152 are read/write and allow the i/o limit address to be located anywhere in the 64-kbyte page (indicated by bits 3116 of the appropriate i/o base) on doubleword boundaries. bits 3116 are read-only and always return 0s when read. the page is set in the i/o base register. bits 1 and 0 are read-only and always return 0s, forcing i/o windows to be aligned on a natural doubleword boundary. write transactions to read-only bits have no effect. the PCI1420 assumes that the lower 2 bits of the limit address are 1s. note: the i/o base or the i/o limit register must be nonzero to enable an i/o transaction. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name i/o limit registers 0, 1 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name i/o limit registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: i/o limit registers 0, 1 type: read-only, read/write offset: 30h, 38h default: 0000 0000h 4.23 interrupt line register the interrupt line register communicates interrupt line routing information. each PCI1420 function has an interrupt line register. bit 7 6 5 4 3 2 1 0 name interrupt line type r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 register: interrupt line type: read/write offset: 3ch default: ffh
413 4.24 interrupt pin register the value read from the interrupt pin register is function dependent and depends on the interrupt signaling mode, selected through bits 21 (intmode field) of the device control register (see section 4.33) and the state of bit 29 (intrtie) in the system control register (see section 4.29). when the intrtie bit is set, this register reads 0x01 (inta ) for both functions. see table 45 for the complete description of the register contents. bit 7 6 5 4 3 2 1 0 name interrupt pin type r r r r r r r r default 0 0 0 0 0 0 1 1 register: interrupt pin type: read-only offset: 3dh default: 03h table 45. interrupt pin register cross reference interrupt signaling mode intrtie bit intpin function 0 intpin function 1 parallel pci interrupts only 0 0x01 (inta ) 0x02 (intb ) parallel irq and parallel pci interrupts 0 0x01 (inta ) 0x02 (intb ) irq serialized (irqser) and parallel pci interrupts 0 0x01 (inta ) 0x02 (intb ) irq and pci serialized (irqser) interrupts (default) 0 0x01 (inta ) 0x02 (intb ) parallel pci interrupts only 1 0x01 (inta ) 0x01 (inta ) parallel irq and parallel pci interrupts 1 0x01 (inta ) 0x01 (inta ) irq serialized (irqser) and parallel pci interrupts 1 0x01 (inta ) 0x01 (inta ) irq and pci serialized (irqser) interrupts 1 0x01 (inta ) 0x01 (inta )
414 4.25 bridge control register the bridge control register provides control over various PCI1420 bridging functions. some bits in this register are global and are accessed only through function 0. see table 46 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bridge control type r r r r r r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w default 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 register: bridge control type: read-only, read/write offset: 3eh (functions 0, 1) default: 0340h table 46. bridge control register bit signal type function 1511 rsvd r reserved. bits 1511 return 0s when read. 10 posten r/w write posting enable. enables write posting to and from the cardbus sockets. write posting enables posting of write data on burst cycles. operating with write posting disabled inhibits performance on burst cycles. note that bursted write data can be posted, but various write transactions may not. bit 10 is socket dependent and is not shared between functions 0 and 1. 9 prefetch1 r/w memory window 1 type. bit 9 specifies whether or not memory window 1 is prefetchable. this bit is socket dependent. bit 9 is encoded as: 0 = memory window 1 is nonprefetchable. 1 = memory window 1 is prefetchable (default). 8 prefetch0 r/w memory window 0 type. bit 8 specifies whether or not memory window 0 is prefetchable. this bit is encoded as: 0 = memory window 0 is nonprefetchable. 1 = memory window 0 is prefetchable (default). 7 intr r/w pci interrupt ireq routing enable. bit 7 selects whether pc card functional interrupts are routed to pci interrupts or the irq specified in the exca registers. 0 = functional interrupts routed to pci interrupts (default) 1 = functional interrupts routed by excas 6 crst r/w cardbus reset. when bit 6 is set, crst is asserted on the cardbus interface. crst can also be asserted by passing a prst assertion to cardbus. 0 = crst deasserted 1 = crst asserted (default) 5 2 mabtmode r/w master abort mode. bit 5 controls how the PCI1420 responds to a master abort when the PCI1420 is an initiator on the cardbus interface. this bit is common between each socket. 0 = master aborts not reported (default) 1 = signal target abort on pci and serr (if enabled) 4 rsvd r reserved. bit 4 returns 0 when read. 3 vgaen r/w vga enable. bit 3 affects how the PCI1420 responds to vga addresses. when this bit is set, accesses to vga addresses are forwarded. 2 isaen r/w isa mode enable. bit 2 affects how the PCI1420 passes i/o cycles within the 64-kbyte isa range. this bit is not common between sockets. when this bit is set, the PCI1420 does not forward the last 768 bytes of each 1k i/o range to cardbus. 1 2 cserren r/w cserr enable. bit 1 controls the response of the PCI1420 to cserr signals on the cardbus bus. this bit is common between the two sockets. 0 = cserr is not forwarded to pci serr . 1 = cserr is forwarded to pci serr . 0 2 cperren r/w cardbus parity error response enable. bit 0 controls the response of the PCI1420 to cardbus parity errors. this bit is common between the two sockets. 0 = cardbus parity errors are ignored. 1 = cardbus parity errors are reported using cperr . 2 this bit is global and is accessed only through function 0.
415 4.26 subsystem vendor id register the subsystem vendor id register is used for system and option-card identification purposes and may be required for certain operating systems. this register is read-only or read/write, depending on the setting of bit 5 (subsysrw) in the system control register (see section 4.29). bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name subsystem vendor id type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: subsystem vendor id type: read-only (read/write if enabled by subsysrw) offset: 40h (functions 0, 1) default: 0000h 4.27 subsystem id register the subsystem id register is used for system and option-card identification purposes and may be required for certain operating systems. this register is read-only or read/write, depending on the setting of bit 5 (subsysrw) in the system control register (see section 4.29). bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name subsystem id type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: subsystem id type: read-only (read/write if enabled by subsysrw) offset: 42h (functions 0, 1) default: 0000h 4.28 pc card 16-bit i/f legacy-mode base address register the PCI1420 supports the index/data scheme of accessing the exca registers, which is mapped by this register. an address written to this register is the address for the index register and the address + 1 is the data address. using this access method, applications requiring index/data exca access can be supported. the base address can be mapped anywhere in 32-bit i/o space on a word boundary; hence, bit 0 is read-only, returning 1 when read. as specified in the pci to pcmcia cardbus bridge register description (yenta), this register is shared by functions 0 and 1. see section 5, exca compatibility registers , for register offsets. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pc card 16-bit i/f legacy-mode base address type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pc card 16-bit i/f legacy-mode base address type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 register: pc card 16-bit i/f legacy-mode base address type: read-only, read/write offset: 44h (functions 0, 1) default: 0000 0001h
416 4.29 system control register system-level initializations are performed through programming this doubleword register. some of the bits are global and are written only through function 0. see table 47 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name system control type r/w r/w r/w r r/w r/w r/c r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name system control type r/w r/w r r r r r r r r/w r/w r/w r/w r/w r/w r/w default 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 register: system control type: read-only, read/write, read/write to clear offset: 80h (functions 0, 1) default: 0044 9060h
417 table 47. system control register bit signal type function 3130 2 ser_step r/w serialized pci interrupt routing step. bits 31 and 30 configure the serialized pci interrupt stream signaling and accomplish an even distribution of interrupts signaled on the four pci interrupt slots. bits 31 and 30 are global to all PCI1420 functions. 00 = inta /intb signal in inta /intb irqser slots 01 = inta /intb signal in intb /intc irqser slots 10 = inta /intb signal in intc /intd irqser slots 11 = inta /intb signal in intd /inta irqser slots 29 2 intrtie r/w tie internal pci interrupts. when this bit is set, the inta and intb signals are tied together internally and are signaled as inta . inta can then be shifted by using bits 3130 (ser_step). this bit is global to all PCI1420 functions. when configuring the PCI1420 functions to share pci interrupts, multifunction terminal mfunc3 must be configured as irqser prior to setting the intrtie bit. 28 rsvd r reserved. bit 28 returns 0 when read. 27 2 p2cclk r/w p2c power switch clock. the PCI1420's clock is used to clock the serial interface power switch and the internal state machine. the default state for bit 27 is 0, requiring an external clock source provided to the clock pin (pin number e19 for the ghk package or pin number 151 for the pdv package). bit 27 can be set to 1 allowing the internal oscillator to provide the clock signal. 0 = clock provided externally, input to PCI1420 (default) 1 = clock generated by internal oscillator and driven by PCI1420. 26 smiroute r/w smi interrupt routing. bit 26 is shared between functions 0 and 1, and selects whether irq2 or csc is signaled when a write occurs to power a pc card socket. 0 = pc card power change interrupts routed to irq2 (default) 1 = a csc interrupt is generated on pc card power changes. 25 smistatus r/c smi interrupt status. this socket-dependent bit is set when bit 24 (smienb) is set and a write occurs to set the socket power. writing a 1 to bit 25 clears the status. 0 = smi interrupt signaled (default) 1 = smi interrupt not signaled 24 2 smienb r/w smi interrupt mode enable. when bit 24 is set and a write to the socket power control occurs, the smi interrupt signaling is enabled and generates an interrupt. this bit is shared and defaults to 0 (disabled). 23 pcipmen r/w pci bus power management interface specification revision 1.1 enable. 0 = use pci bus power management interface specification revision 1.0 implementation (default) 1 = use pci bus power management interface specification revision 1.1 implementation 22 cbrsvd r/w cardbus reserved terminals signaling. when a cardbus card is inserted and bit 22 is set, the rsvd cardbus terminals are driven low. when this bit is 0, these signals are placed in a high-impedance state. 0 = 3-state cardbus rsvd 1 = drive cardbus rsvd low (default) 21 vccprot r/w v cc protection enable. bit 21 is socket dependent. 0 = v cc protection enabled for 16-bit cards (default) 1 = v cc protection disabled for 16-bit cards 20 reducezv r/w reduced zoomed video enable. when this bit is enabled, pins a25a22 of the card interface for pc card-16 cards are placed in the high-impedance state. this bit should not be set for normal zv operation. this bit is encoded as: 0 = reduced zoomed video disabled (default) 1 = reduced zoomed video enabled 19 cdreqen r/w pc/pci dma card enable. when bit 19 is set, the PCI1420 allows 16-bit pc cards to request pc/pci dma using the dreq signaling. dreq is selected through the socket dma register 0. 0 = ignore dreq signaling from pc cards (default) 1 = signal dma request on dreq 1816 cdmachan r/w pc/pci dma channel assignment. bits 1816 are encoded as: 03 = 8-bit dma channels 4 = pci master; not used (default). 57 = 16-bit dma channels 2 this bit is global and is accessed only through function 0.
418 table 47. system control register (continued) bit signal type function 15 2 mrburstdn r/w memory read burst enable downstream. when bit 15 is set, memory read transactions are allowed to burst downstream. 0 = downstream memory read burst is disabled. 1 = downstream memory read burst is enabled (default). 14 2 mrburstup r/w memory read burst enable upstream. when bit 14 is set, the PCI1420 allows memory read transactions to burst upstream. 0 = upstream memory read burst is disabled (default). 1 = upstream memory read burst is enabled. 13 socactive r socket activity status. when set, bit 13 indicates access has been performed to or from a pc card and is cleared upon read of this status bit. this bit is socket-dependent. 0 = no socket activity (default) 1 = socket activity 12 rsvd r reserved. bit 12 returns 1 when read. 11 2 pwrstream r power stream in progress status bit. when set, bit 11 indicates that a power stream to the power switch is in progress and a powering change has been requested. this bit is cleared when the power stream is complete. 0 = power stream is complete and delay has expired. 1 = power stream is in progress. 10 2 delayup r power-up delay in progress status. when set, bit 9 indicates that a power-up stream has been sent to the power switch and proper power may not yet be stable. this bit is cleared when the power-up delay has expired. 9 2 delaydown r power-down delay in progress status. when set, bit 10 indicates that a power-down stream has been sent to the power switch and proper power may not yet be stable. this bit is cleared when the power-down delay has expired. 8 interrogate r interrogation in progress. when set, bit 8 indicates an interrogation is in progress and clears when interrogation completes. this bit is socket dependent. 0 = interrogation not in progress (default) 1 = interrogation in progress 7 rsvd r reserved. bit 7 returns 0 when read. 6 pwrsavings r/w power savings mode enable. when this bit is set, if a cb card is inserted, idle, and without a cb clock, then the applicable cb state machine will not be clocked. 5 2 subsysrw r/w subsystem id (see section 4.27), subsystem vendor id (see section 4.26), exca identification and revision (see section 5.1) registers read/write enable. bit 5 is shared by functions 0 and 1. 0 = subsystem id, subsystem vendor id, exca identification and revision registers are read/write. 1 = subsystem id, subsystem vendor id, exca identification and revision registers are read-only (default). 4 2 cb_dpar r/w cardbus data parity serr signaling enable 0 = cardbus data parity not signaled on pci serr 1 = cardbus data parity signaled on pci serr 3 2 cdma_en r/w pc/pci dma enable. bit 3 enables pc/pci dma when set if mfunc0mfunc6 are configured for centralized dma. 0 = centralized dma disabled (default) 1 = centralized dma enabled 2 excapower r/w exca power control bit. 0 = enables 3.3 v 1 = enables 5 v 1 2 keepclk r/w keep clock. this bit works with pci and cb clkrun protocols. 0 = allows normal functioning of both clkrun protocols.(default) 1 = does not allow cb clock or pci clock to be stopped using the clkrun protocols. 0 rimux r/w ri_out /pme multiplex enable. 0 = ri_out and pme are both routed to the ri_out /pme terminal. if both are enabled at the same time, then ri_out has precedence over pme . 1 = only pme is routed to the ri_out /pme terminal. 2 this bit is global and is accessed only through function 0.
419 4.30 multifunction routing register the multifunction routing register is used to configure the mfunc0mfunc6 terminals. these terminals may be configured for various functions. all multifunction terminals default to the general-purpose input configuration. this register is intended to be programmed once at power-on initialization. the default value for this register may also be loaded through a serial bus eeprom. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name multifunction routing type r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name multifunction routing type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: multifunction routing type: read-only, read/write offset: 8ch (functions 0, 1) default: 0000 0000h table 48. multifunction routing register bit signal type function 3128 rsvd r bits 3128 return 0s when read. 2724 mfunc6 r/w multifunction terminal 6 configuration. these bits control the internal signal mapped to the mfunc6 terminal as follows: 0000 = rsvd 0100 = irq4 1000 = irq8 1100 = irq12 0001 = clkrun 0101 = irq5 1001 = irq9 1101 = irq13 0010 = irq2 0110 = irq6 1010 = irq10 1110 = irq14 0011 = irq3 0111 = irq7 1011 = irq11 1111 = irq15 2320 mfunc5 r/w multifunction terminal 5 configuration. these bits control the internal signal mapped to the mfunc5 terminal as follows: 0000 = gpi4 0100 = irq4 1000 = caudpwm 1100 = leda1 0001 = gpo4 0101 = irq5 1001 = rsvd 1101 = led_skt 0010 = pcgnt 0110 = zvstat 1010 = irq10 1110 = gpe 0011 = irq3 0111 = zvsel1 1011 = irq11 1111 = irq15 1916 mfunc4 r/w multifunction terminal 4 configuration. these bits control the internal signal mapped to the mfunc4 terminal as follows: note: when the serial bus mode is implemented by pulling down the latch terminal, the mfunc4 terminal provides the scl signaling. 0000 = gpi3 0100 = irq4 1000 = caudpwm 1100 = ri_out 0001 = gpo3 0101 = irq5 1001 = irq9 1101 = led_skt 0010 = lock pci 0110 = zvstat 1010 = irq10 1110 = gpe 0011 = irq3 0111 = zvsel1 1011 = irq11 1111 = rsvd 1512 mfunc3 r/w multifunction terminal 3 configuration. these bits control the internal signal mapped to the mfunc3 terminal as follows: 0000 = rsvd 0100 = irq4 1000 = irq8 1100 = irq12 0001 = irqser 0101 = irq5 1001 = irq9 1101 = irq13 0010 = irq2 0110 = irq6 1010 = irq10 1110 = irq14 0011 = irq3 0111 = irq7 1011 = irq11 1111 = irq15 118 mfunc2 r/w multifunction terminal 2 configuration. these bits control the internal signal mapped to the mfunc2 terminal as follows: 0000 = gpi2 0100 = irq4 1000 = caudpwm 1100 = ri_out 0001 = gpo2 0101 = irq5 1001 = irq9 1101 = leda2 0010 = pcreq 0110 = zvstat 1010 = irq10 1110 = gpe 0011 = irq3 0111 = zvsel0 1011 = rsvd 1111 = irq7
420 table 48. multifunction routing register (continued) bit signal type function 74 mfunc1 r/w multifunction terminal 1 configuration. these bits control the internal signal mapped to the mfunc1 terminal as follows: note: when the serial bus mode is implemented by pulling down the latch terminal, the mfunc1 terminal provides the sda signaling. 0000 = gpi1 0100 = irq4 1000 = caudpwm 1100 = leda1 0001 = gpo1 0101 = irq5 1001 = irq9 1101 = leda2 0010 = intb 0110 = zvstat 1010 = irq10 1110 = gpe 0011 = irq3 0111 = zvsel0 1011 = irq11 1111 = irq15 30 mfunc0 r/w multifunction terminal 0 configuration. these bits control the internal signal mapped to the mfunc0 terminal as follows: 0000 = gpi0 0100 = irq4 1000 = caudpwm 1100 = leda1 0001 = gpo0 0101 = irq5 1001 = irq9 1101 = leda2 0010 = inta 0110 = zvstat 1010 = irq10 1110 = gpe 0011 = irq3 0111 = zvsel0 1011 = irq11 1111 = irq15
421 4.31 retry status register the retry status register enables the retry timeout counters and displays the retry expiration status. the flags are set when the PCI1420 retries a pci or cardbus master request and the master does not return within 2 15 pci clock cycles. the flags are cleared by writing a 1 to the bit. these bits are expected to be incorporated into the pci command, pci status, and bridge control registers by the pci sig. access this register only through function 0. see table 49 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name retry status type r/w r/w r/c r r/c r r/c r default 1 1 0 0 0 0 0 0 register: retry status type: read-only, read/write, read/write to clear offset: 90h (functions 0, 1) default: c0h table 49. retry status register bit signal type function 7 pciretry r/w pci retry timeout counter enable. bit 7 is encoded: 0 = pci retry counter disabled 1 = pci retry counter enabled (default) 6 2 cbretry r/w cardbus retry timeout counter enable. bit 6 is encoded: 0 = cardbus retry counter disabled 1 = cardbus retry counter enabled (default) 5 texp_cbb r/c cardbus target b retry expired. write a 1 to clear bit 5. 0 = inactive (default) 1 = retry has expired 4 rsvd r reserved. bit 4 returns 0 when read. 3 2 texp_cba r/c cardbus target a retry expired. write a 1 to clear bit 3. 0 = inactive (default) 1 = retry has expired. 2 rsvd r reserved. bit 2 returns 0 when read. 1 texp_pci r/c pci target retry expired. write a 1 to clear bit 1. 0 = inactive (default) 1 = retry has expired. 0 rsvd r reserved. bit 0 returns 0 when read. 2 this bit is global and is accessed only through function 0.
422 4.32 card control register the card control register is provided for pci1130 compatibility. ri_out is enabled through this register, and the enable bit is shared between functions 0 and 1. see table 410 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name card control type r/w r/w r/w r r r/w r/w r/c default 0 0 0 0 0 0 0 0 register: card control type: read-only, read/write, read/write to clear offset: 91h default: 00h table 410. card control register bit signal type function 7 2 rienb r/w ring indicate output enable. 0 = disables any routing of ri_out signal (default). 1 = enables ri_out signal for routing to the ri_out /pme terminal, when rimux is set to 0, and for routing to mfunc2 or mfunc4. 6 zvenable r/w compatibility zv mode enable. when set, the corresponding pc card socket interface zv terminals enter a high-impedance state. this bit defaults to 0. 5 port_sel r/w port select. this bit controls the priority for the zvsel0 and zvsel1 signaling if bit 6 (zvenable) is set in both functions. 0 = socket 0 takes priority, as signaled through zvsel0 , when both sockets are in zv mode. 1 = socket 1 takes priority, as signaled through zvsel1 , when both sockets are in zv mode. 43 rsvd r reserved. bits 4 and 3 return 0 when read. 2 aud2mux r/w cardbus audio-to-irqmux. when set, the caudio cardbus signal is routed to the corresponding multifunction terminal which may be configured for caudpwm. when both socket 0 and 1 functions have aud2mux set, socket 0 takes precedence. 1 spkrouten r/w speaker out enable. when bit 1 is set, spkr on the pc card is enabled and is routed to spkrout. the spkr signal from socket 0 is exclusive ored with the spkr signal from socket 1 and sent to spkrout. the spkrout terminal drives data only when either function's spkrouten bit is set. this bit is encoded as: 0 = spkr to spkrout not enabled 1 = spkr to spkrout enabled 0 ifg r/c interrupt flag. bit 0 is the interrupt flag for 16-bit i/o pc cards and for cardbus cards. bit 0 is set when a functional interrupt is signaled from a pc card interface and is socket dependent (that is, not global). write back a 1 to clear this bit. 0 = no pc card functional interrupt detected (default). 1 = pc card functional interrupt detected. 2 this bit is global and is accessed only through function 0.
423 4.33 device control register the device control register is provided for pci1130 compatibility and contains bits that are shared between functions 0 and 1. the interrupt mode select is programmed through this register which is composed of PCI1420 global bits. the socket-capable force bits are also programmed through this register. see table 411 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name device control type r/w r/w r/w r r/w r/w r/w r/w default 0 1 1 0 0 1 1 0 register: device control type: read-only, read/write offset: 92h (functions 0, 1) default: 66h table 411. device control register bit signal type function 7 sktpwr_lock r/w socket power lock bit. when this bit is set to 1, software will not be able to power down the pc card socket while in d3. this may be necessary to support wake on lan or ring if the operating system is programmed to power down a socket when the cardbus controller is placed in the d3 state. 6 2 3vcapable r/w 3-v socket capable force 0 = not 3-v capable 1 = 3-v capable (default) 5 io16v2 r/w diagnostic bit. this bit defaults to 1. 4 rsvd r reserved. bit 4 returns 0 when read. 3 2 test r/w ti test. only a 0 should be written to bit 3. 21 intmode r/w interrupt signaling mode. bits 2 and 1 select the interrupt signaling mode. the interrupt signaling mode bits are encoded: 00 = parallel pci interrupts only 01 = parallel irq and parallel pci interrupts 10 = irq serialized interrupts and parallel pci interrupt 11 = irq and pci serialized interrupts (default) 0 2 rsvd r/w reserved. bit 0 is reserved for test purposes. only 0 should be written to this bit. 2 this bit is global and is accessed only through function 0.
424 4.34 diagnostic register the diagnostic register is provided for internal ti test purposes. it is a read/write register, but only 0s should be written to it. see table 412 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name diagnostic type r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 1 0 0 0 0 1 register: diagnostic type: read/write offset: 93h (functions 0, 1) default: 61h table 412. diagnostic register bit signal type function 7 2 true_val r/w this bit defaults to 0. this bit is encoded as: 0 = reads true values in pci vendor id and pci device id registers (default) 1 = reads all 1s in reads to the pci vendor id and pci device id registers 6 aospmen r/w auto oscillator enable. this bit provides fail safe for the oscillator power management logic. if the problem arises with the logic, then this bit disables all the power management features of the oscillator. this bit is encoded as: 0 = oscillator power management features enabled (default) 1 = oscillator power management features disabled 5 csc r/w csc interrupt routing control 0 = csc interrupts routed to pci if exca 803 bit 4 = 1 1 = csc interrupts routed to pci if exca 805 bits 74 = 0000b. (default) in this case, the setting of exca 803 bit 4 is a adon't careo 4 2 diag4 r/w diagnostic retry_dis. delayed transaction disable. 3 2 diag3 r/w diagnostic retry_ext. extends the latency from 16 to 64. 2 2 diag2 r/w diagnostic discard_tim_sel_cb. set = 2 10 , reset = 2 15 . 1 2 diag1 r/w diagnostic discard_tim_sel_pci. set = 2 10 , reset = 2 15 . 0 async r/w asynchronous interrupt enable. 0 = csc interrupt is not generated asynchronously 1 = csc interrupt is generated asynchronously (default) 2 this bit is global and is accessed only through function 0.
425 4.35 socket dma register 0 the socket dma register 0 provides control over the pc card dma request (dreq ) signaling. see table 413 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket dma register 0 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket dma register 0 type r r r r r r r r r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket dma register 0 type: read-only, read/write offset: 94h (functions 0, 1) default: 0000 0000h table 413. socket dma register 0 bit signal type function 312 rsvd r reserved. bits 312 return 0s when read. 10 dreqpin r/w dma request (dreq ). bits 1 and 0 indicate which pin on the 16-bit pc card interface acts as dreq during dma transfers. this field is encoded as: 00 = socket not configured for dma (default). 01 = dreq uses spkr . 10 = dreq uses iois16 . 11 = dreq uses inpack .
426 4.36 socket dma register 1 the socket dma register 1 provides control over the distributed dma (ddma) registers and the pci portion of dma transfers. the dma base address locates the ddma registers in a 16-byte region within the first 64k bytes of pci i/o address space. see table 414 for a complete description of the register contents. note: 32-bit transfers are not supported; the maximum transfer possible for 16-bit pc cards is 16 bits. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket dma register 1 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket dma register 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket dma register 1 type: read-only, read/write offset: 98h (functions 0, 1) default: 0000 0000h table 414. socket dma register 1 bit signal type function 3116 rsvd r reserved. bits 3116 return 0s when read. 154 dmabase r/w dma base address. locates the socket's dma registers in pci i/o space. this field represents a 16-bit pci i/o address. the upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64k bytes of i/o address space. the lower 4 bits are hardwired to 0 and are included in the address decode. thus, the window is aligned to a natural 16-byte boundary. 3 extmode r extended addressing. this feature is not supported by the PCI1420 and always returns a 0. 21 xfersize r/w transfer size. bits 2 and 1 specify the width of the dma transfer on the pc card interface and are encoded as: 00 = transfers are 8 bits (default). 01 = transfers are 16 bits. 10 = reserved 11 = reserved 0 ddmaen r/w ddma registers decode enable. enables the decoding of the distributed dma registers based on the value of dmabase. 0 = disabled (default) 1 = enabled
427 4.37 capability id register the capability id register identifies the linked list item as the register for pci power management. the register returns 01h when read, which is the unique id assigned by the pci sig for the pci location of the capabilities pointer and the value. bit 7 6 5 4 3 2 1 0 name capability id type r r r r r r r r default 0 0 0 0 0 0 0 1 register: capability id type: read-only offset: a0h default: 01h 4.38 next-item pointer register the next-item pointer register indicates the next item in the linked list of the pci power management capabilities. because the PCI1420 functions include only one capabilities item, this register returns 0s when read. bit 7 6 5 4 3 2 1 0 name next-item pointer type r r r r r r r r default 0 0 0 0 0 0 0 0 register: next-item pointer type: read-only offset: a1h default: 00h
428 4.39 power management capabilities register this register contains information on the capabilities of the pc card function related to power management. both PCI1420 cardbus bridge functions support d0, d1, d2, and d3 power states. see table 415 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name power management capabilities type r/w r r r r r r r r r r r r r r r default 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 register: power management capabilities type: read/write, read-only offset: a2h default: fe11h table 415. power management capabilities register bit signal type function pme support. this 5-bit field indicates the power states from which the PCI1420 device functions may assert pme . a 0 (zero) for any bit indicates that the function cannot assert the pme signal while in that power state. these five bits return 1 1111b when read. each of these bits is described below: 15 pme_support r/w bit 15 defaults to the value 1 indicating the pme signal can be asserted from the d3 cold state. this bit is r/w because wake-up support from d3 cold is contingent on the system providing an auxiliary power source to the v cc terminals. if the system designer chooses not to provide an auxiliary power source to the v cc terminals for d3 cold wake-up support, then bios should write a 0 to this bit. 1411 pme_support r bit 14 contains the value 1, indicating that the pme signal can be asserted from d3 hot state. bit 13 contains the value 1, indicating that the pme signal can be asserted from d2 state. bit 12 contains the value 1, indicating that the pme signal can be asserted from d1 state. bit 11 contains the value 1, indicating that the pme signal can be asserted from the d0 state. 10 d2_support r d2 support. bit 10 returns a 1 when read, indicating that the cardbus function supports the d2 device power state. 9 d1_support r d1 support. bit 9 returns a 1 when read, indicating that the cardbus function supports the d1 device power state. 86 rsvd r reserved. bits 86 return 0s when read. 5 dsi r device-specific initialization. bit 5 returns 1 when read, indicating that the cardbus controller function require special initialization (beyond the standard pci configuration header) before the generic class device driver is able to use it. 4 aux_pwr r auxiliary power source. bit 4 is meaningful only if bit 15 (pme_support, d3 cold ) is set. when bit 4 is set, it indicates that support for pme in d3 cold requires auxiliary power supplied by the system by way of a proprietary delivery vehicle. when bit 4 is 0, it indicates that the function supplies its own auxiliary power source. 3 pmeclk r pme clock. bit 3 returns 0 when read, indicating that no host bus clock is required for the PCI1420 to generate pme . 20 version r version. bits 20 return 001b when read, indicating that there are four bytes of general-purpose power management (pm) registers as described in the pci bus power management interface specification .
429 4.40 power management control/status register the power management control/status register determines and changes the current power state of the PCI1420 cardbus function. the contents of this register are not affected by the internally-generated reset caused by the transition from d3 hot to d0 state. all pci, exca, and cardbus registers are reset as a result of a d3 hot to d0 state transition. ti-specific registers, pci power management registers, and the legacy base address register are not reset. see table 416 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name power management control/status type r/c r r r r r r r/w r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: power management control/status type: read-only, read/write, read/write to clear offset: a4h (functions 0, 1) default: 0000h table 416. power management control/status register bit signal type function 15 pmestat r/c pme status. bit 15 is set when the cardbus function would normally assert pme , independent of the state of bit 8 (pme_en). bit 15 is cleared by a write back of 1, and this also clears the pme signal if pme was asserted by this function. writing a 0 to this bit has no effect. 1413 datascale r data scale. this 2-bit field returns 0s when read. the cardbus function does not return any dynamic data. 129 datasel r data select. this 4-bit field returns 0s when read. the cardbus function does not return any dynamic data. 8 pme_en r/w pme enable. bit 8 enables the function to assert pme . if this bit is cleared, then assertion of pme is disabled. 72 rsvd r reserved. bits 72 return 0s when read. 10 pwr_state r/w power state. this 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. this field is encoded as: 00 = d0 01 = d1 10 = d2 11 = d3 hot
430 4.41 power management control/status register bridge support extensions the power management control/status register bridge support extensions support pci bridge specific functionality. see table 417 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name power management control/status register bridge support extensions type r r r r r r r r default 1 1 0 0 0 0 0 0 register: power management control/status register bridge support extensions type: read-only offset: a6h (functions 0, 1) default: c0h table 417. power management control/status register bridge support extensions bit signal type function 7 bpcc_en r bpcc_enable. bus power/clock control enable. this bit returns 1 when read. this bit is encoded as: 0 = bus power/clock control is disabled. 1 = bus power/clock control is enabled (default). a 0 indicates that the bus power/clock control policies defined in the pci bus power management interface specification are disabled. when the bus power/clock control enable mechanism is disabled, the bridge's power management control/status register power state field (see section 4.40, bits 10) cannot be used by the system software to control the power or the clock of the bridge's secondary bus. a 1 indicates that the bus power/clock control mechanism is enabled. 6 b2_b3 r b2/b3 support for d3 hot . the state of this bit determines the action that is to occur as a direct result of programming the function to d3 hot . this bit is only meaningful if bit 7 (bpcc_en) is a 1. this bit is encoded as: 0 = when the bridge is programmed to d3 hot , its secondary bus will have its power removed (b3). 1 = when the bridge function is programmed to d3 hot , its secondary bus's pci clock will be stopped (b2). (default) 50 rsvd r reserved. bits 50 return 0s when read. 4.42 power management data register the power management data register returns 0s when read, since the cardbus functions do not report dynamic data. bit 7 6 5 4 3 2 1 0 name power management data type r r r r r r r r default 0 0 0 0 0 0 0 0 register: power management data type: read-only offset: a7h (functions 0, 1) default: 00h
431 4.43 general-purpose event status register the general-purpose event status register contains status bits that are set when events occur that are controlled by the general-purpose control register. the bits in this register and the corresponding gpe are cleared by writing a 1 to the corresponding bit location. the status bits in this register do not depend upon the state of a corresponding bit in the general-purpose enable register. access this register only through function 0. see table 418 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name general-purpose event status type r/c r/c r r r/c r r r/c r r r r/c r/c r/c r/c r/c default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: general-purpose event status type: read-only, read/write to clear offset: a8h (function 0) default: 0000h table 418. general-purpose event status register bit signal type function 15 zv0_sts r/c pc card socket 0 zv status. bit 15 is set on a change in status of bit 6 (zvenable) in the function 0 pc card controller function (see section 4.32). 14 zv1_sts r/c pc card socket 1 zv status. bit 14 is set on a change in status of bit 6 (zvenable) in the function 1 pc card controller function (see section 4.32). 1312 rsvd r reserved. bits 13 and 12 return 0s when read. 11 pwr_sts r/c power change status. bit 11 is set when software has changed the power state of either socket. a change in either v cc or v pp for either socket causes this bit to be set. 109 rsvd r reserved. bits 10 and 9 return 0s when read. 8 vpp12_sts r/c 12-volt v pp request status. bit 8 is set when software has changed the requested vpp level to or from 12 volts for either of the 2 pc card sockets. 75 rsvd r reserved. bits 75 return 0s when read. 4 gp4_sts r/c gpi4 status. bit 4 is set on a change in status of the mfunc5 terminal input level. 3 gp3_sts r/c gpi3 status. bit 3 is set on a change in status of the mfunc4 terminal input level . 2 gp2_sts r/c gpi2 status. bit 2 is set on a change in status of the mfunc2 terminal input level. 1 gp1_sts r/c gpi1 status. bit 1 is set on a change in status of the mfunc1 terminal input level. 0 gp0_sts r/c gpi0 status. bit 0 is set on a change in status of the mfunc0 terminal input level.
432 4.44 general-purpose event enable register the general-purpose event enable register contains bits that are set to enable a gpe signal. the gpe signal is driven until the corresponding status bit is cleared and the event is serviced. the gpe can only be signaled if one of the multifunction terminals, mfunc6mfunc0, is configured for gpe signaling. access this register only through function 0. see table 419 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name general-purpose event enable type r/w r/w r r r/w r r r/w r r r r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: general-purpose event enable type: read-only, read/write offset: aah (function 0) default: 0000h table 419. general-purpose event enable register bit signal type function 15 zv0_en r/w pc card socket 0 zv enable. when bit 15 is set, a gpe is signaled on a change in status of bit 6 (zvenable) in the function 0 pc card controller function (see section 4.32). 14 zv1_en r/w pc card socket 1 zv enable. when bit 14 is set, a gpe is signaled on a change in status of bit 6 (zvenable) in the function 1 pc card controller function (see section 4.32). 1312 rsvd r reserved. bits 13 and 12 return 0s when read. 11 pwr_en r/w power change enable. when bit 11 is set, a gpe is signaled on when software has changed the power state of either socket. 109 rsvd r reserved. bits 10 and 9 return 0s when read. 8 vpp12_en r/w 12 volt v pp request enable. when bit 8 is set, a gpe is signaled when software has changed the requested v pp level to or from 12 volts for either card socket. 75 rsvd r reserved. bits 75 return 0s when read. 4 gp4_en r/w gpi4 enable. when bit 4 is set, a gpe is signaled when there has been a change in status of the mfunc5 terminal input level if configured as gpi4. 3 gp3_en r/w gpi3 enable. when bit 3 is set, a gpe is signaled when there has been a change in status of the mfunc4 terminal input level if configured as gpi3. 2 gp2_en r/w gpi2 enable. when bit 2 is set, a gpe is signaled when there has been a change in status of the mfunc2 terminal input if configured as gpi2. 1 gp1_en r/w gpi1 enable. when bit 1 is set, a gpe is signaled when there has been a change in status of the mfunc1 terminal input if configured as gpi1. 0 gp0_en r/w gpi0 enable. when bit 0 is set, a gpe is signaled when there has been a change in status of the mfunc0 terminal input if configured as gpi0.
433 4.45 general-purpose input register the general-purpose input register provides the logical value of the data input from the gpi terminals, mfunc5, mfunc4, and mfunc2mfunc0. access this register only through function 0. see table 420 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name general-purpose input type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 x x x x x register: general-purpose input type: read-only offset: ach (function 0) default: 00xxh table 420. general-purpose input register bit signal type function 155 rsvd r reserved. bits 155 return 0s when read. 4 gpi4_data r gpi4 data bit. the value read from bit 4 represents the logical value of the data input from the mfunc5 terminal. 3 gpi3_data r gpi3 data bit. the value read from bit 3 represents the logical value of the data input from the mfunc4 terminal. 2 gpi2_data r gpi2 data bit. the value read from bit 2 represents the logical value of the data input from the mfunc2 terminal. 1 gpi1_data r gpi1 data bit. the value read from bit 1 represents the logical value of the data input from the mfunc1 terminal. 0 gpi0_data r gpi0 data bit. the value read from bit 0 represents the logical value of the data input from the mfunc0 terminal.
434 4.46 general-purpose output register the general-purpose output register is used for control of the general-purpose outputs. access this register only through function 0. see table 421 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name general-purpose output type r r r r r r r r r r r r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: general-purpose output type: read-only, read/write offset: aeh (function 0) default: 0000h table 421. general-purpose output register bit signal type function 155 rsvd r reserved. bits 155 return 0s when read. 4 gpo4_data r/w gpo4 data bit. the value written to bit 4 represents the logical value of the data driven to the mfunc5 terminal if configured as gpo4. read transactions return the last data value written. 3 gpo3_data r/w gpio3 data bit. the value written to bit 3 represents the logical value of the data driven to the mfunc4 terminal if configured as gpo3. read transactions return the last data value written. 2 gpo2_data r/w gpo2 data bit. the value written to bit 2 represents the logical value of the data driven to the mfunc2 terminal if configured as gpo2. read transactions return the last data value written. 1 gpo1_data r/w gpo1 data bit. the value written to bit 1 represents the logical value of the data driven to the mfunc1 terminal if configured as gpo1. read transactions return the last data value written. 0 gpo0_data r/w gpo0 data bit. the value written to bit 0 represents the logical value of the data driven to the mfunc0 terminal if configured as gpo0. read transactions return the last data value written. 4.47 serial bus data register the serial bus data register is for programmable serial bus byte reads and writes. this register represents the data when generating cycles on the serial bus interface. to write a byte, this register must be programmed with the data, the serial bus index register must be programmed with the byte address, the serial bus slave address must be programmed with both the 7-bit slave address, and the read/write indicator bit must be reset. on byte reads, the byte address is programmed into the serial bus index register , the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator bit must be set, and bit 5 (reqbusy) in the serial bus control and status register (see section 4.50) must be polled until clear. then the contents of this register are valid read data from the serial bus interface. see table 422 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name serial bus data type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: serial bus data type: read/write offset: b0h (function 0) default: 00h table 422. serial bus data register bit signal type function 70 sbdata r/w serial bus data. this bit field represents the data byte in a read or write transaction on the serial interface. on reads, the reqbusy bit must be polled to verify that the contents of this register are valid.
435 4.48 serial bus index register the serial bus index register is for programmable serial bus byte reads and writes. this register represents the byte address when generating cycles on the serial bus interface. to write a byte, the serial bus data register must be programmed with the data, this register must be programmed with the byte address, and the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator. on byte reads, the word address is programmed into this register , the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator bit must be set, and bit 5 (reqbusy) in the serial bus control and status register (see section 4.50) must be polled until clear. then the contents of the serial bus data register are valid read data from the serial bus interface. see table 423 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name serial bus index type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: serial bus index type: read/write offset: b1h (function 0) default: 00h table 423. serial bus index register bit signal type function 70 sbindex r/w serial bus index. this bit field represents the byte address in a read or write transaction on the serial interface. 4.49 serial bus slave address register the serial bus slave address register is for programmable serial bus byte read and write transactions. to write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be programmed with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write indicator bit. on byte reads, the byte address is programmed into the serial bus index register , this register must be programmed with both the 7-bit slave address and the read/write indicator bit must be set, and bit 5 (reqbusy) in the serial bus control and status register (see section 4.50) must be polled until clear. then the contents of the serial bus data register are valid read data from the serial bus interface. see table 424 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name serial bus slave address type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: serial bus slave address type: read/write offset: b2h (function 0) default: 00h table 424. serial bus slave address register bit signal type function 71 slavaddr r/w serial bus slave address. this bit field represents the slave address of a read or write transaction on the serial interface. 0 rwcmd r/w read/write command. bit 0 indicates the read/write command bit presented to the serial bus on byte read and write accesses 0 = a byte write access is requested to the serial bus interface 1 = a byte read access is requested to the serial bus interface
436 4.50 serial bus control and status register the serial bus control and status register communicates serial bus status information and select the quick command protocol. bit 5 (reqbusy) in this register must be polled during serial bus byte reads to indicate when data is valid in the serial bus data register. see table 425 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name serial bus control and status type r/w r r r r/c r/w r/c r/c default 0 0 0 0 0 0 0 0 register: serial bus control and status type: read-only, read/write, read/write to clear offset: b3h (function 0) default: 00h table 425. serial bus control and status register bit signal type function 7 prot_sel r/w protocol select. when bit 7 is set, the send byte protocol is used on write requests and the receive byte protocol is used on read commands. the word address byte in the serial bus index register (see section 4.48) is not output by the PCI1420 when bit 7 is set. 6 rsvd r reserved. bit 6 returns 0 when read. 5 reqbusy r requested serial bus access busy. bit 5 indicates that a requested serial bus access (byte read or write) is in progress. a request is made, and bit 5 is set, by writing to the serial bus slave address register (see section 4.49). bit 5 must be polled on reads from the serial interface. after the byte read access has been requested, the read data is valid in the serial bus data register. 4 rombusy r serial eeprom busy status. bit 4 indicates the status of the PCI1420 serial eeprom circuitry. bit 4 is set during the loading of the subsystem id and other default values from the serial bus eeprom. 0 = serial eeprom circuitry is not busy 1 = serial eeprom circuitry is busy 3 sbdetect r/c serial bus detect. when bit 3 is set, it indicates that the serial bus interface is detected. a pulldown resistor must be implemented on the latch terminal for bit 3 to be set. if bit 3 is reset, then the mfunc4 and mfunc1 terminals can be used for alternate functions such as general-purpose inputs and outputs. 0 = serial bus interface not detected 1 = serial bus interface detected 2 sbtest r/w serial bus test. when bit 2 is set, the serial bus clock frequency is increased for test purposes. 0 = serial bus clock at normal operating frequency, 100 khz (default) 1 = serial bus clock frequency increased for test purposes 1 req_err r/c requested serial bus access error. bit 1 indicates when a data error occurs on the serial interface during a requested cycle and may be set due to a missing acknowledge. bit 1 is cleared by a write back of 1. 0 = no error detected during user requested byte read or write cycle 1 = data error detected during user requested byte read or write cycle 0 rom_err r/c eeprom data error status. bit 0 indicates when a data error occurs on the serial interface during the auto-load from the serial bus eeprom and may be set due to a missing acknowledge. bit 0 is also set on invalid eeprom data formats. see section 3.6.1, serial bus interface implementation , for details on eeprom data format. bit 0 is cleared by a write back of 1. 0 = no error detected during auto-load from serial bus eeprom 1 = data error detected during auto-load from serial bus eeprom
51 5 exca compatibility registers (functions 0 and 1) the exca registers implemented in the PCI1420 are register-compatible with the intel 82365sldf pcmcia controller. exca registers are identified by an offset value that is compatible with the legacy i/o index/data scheme used on the intel 82365 isa controller. the exca registers are accessed through this scheme by writing the register offset value into the index register (i/o base) and reading or writing the data register (i/o base + 1). the i/o base address used in the index/data scheme is programmed in the pc card 16-bit i/f legacy mode base address register (see section 4.28), which is shared by both card sockets. the offsets from this base address run contiguous from 00h to 3fh for socket a, and from 40h to 7fh for socket b. see figure 51 for an exca i/o mapping illustration. cardbus socket/exca base address 16-bit legacy-mode base address 10h 44h 00h 3fh offset index host i/o space data pc card a exca registers pc card b exca registers 40h 7fh note: the 16-bit legacy mode base address register is shared by functions 0 and 1 as indicated by the shading. PCI1420 configuration registers offset figure 51. exca register access through i/o the ti PCI1420 also provides a memory mapped alias of the exca registers by directly mapping them into pci memory space. they are located through the cardbus socket registers/exca base address register (see section 4.12) at memory offset 800h. each socket has a separate base address programmable by function. see figure 52 for an exca memory mapping illustration. note that memory offsets are 800h844h for both functions 0 and 1. this illustration also identifies the cardbus socket register mapping, which is mapped into the same 4k window at memory offset 0h.
52 cardbus socket/exca base address 16-bit legacy-mode base address 10h 44h note: the cardbus socket/exca base address mode register is separate for functions 0 and 1. PCI1420 configuration registers cardbus socket a registers host memory space 00h exca registers card a 20h 800h 844h offset cardbus socket b registers host memory space 00h exca registers card b 20h 800h 844h offset offset figure 52. exca register access through memory the interrupt registers, as defined by the 82365sldl specification, in the exca register set control such card functions as reset, type, interrupt routing, and interrupt enables. special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI1420 to ensure that all possible PCI1420 interrupts can potentially be routed to the programmable interrupt controller. the exca registers that are critical to the interrupt signaling are the exca interrupt and general control register (see section 5.4) and the exca card status-change-interrupt configuration register (see section 5.6). access to i/o mapped 16-bit pc cards is available to the host system via two exca i/o windows. these are regions of host i/o address space into which the card i/o space is mapped. these windows are defined by start, end, and offset addresses programmed in the exca registers described in this section. i/o windows have byte granularity. access to memory mapped 16-bit pc cards is available to the host system via five exca memory windows. these are regions of host memory space into which the card memory space is mapped. these windows are defined by start, end, and offset addresses programmed in the exca registers described in this section. table 51 identifies each exca register and its respective exca offset. memory windows have 4k-byte granularity.
53 table 51. exca registers and offsets e x ca register name pci memory address exca offset (hex) e x ca register name offset (hex) card a card b identification and revision 800 00 40 interface status 801 01 41 power control 802 02 42 interrupt and general control 803 03 43 card status change 804 04 44 card status-change-interrupt configuration 805 05 45 address window enable 806 06 46 i / o window control 807 07 47 i / o window 0 start-address low byte 808 08 48 i / o window 0 start-address high byte 809 09 49 i / o window 0 end-address low byte 80a 0a 4a i / o window 0 end-address high byte 80b 0b 4b i / o window 1 start-address low byte 80c 0c 4c i / o window 1 start-address high byte 80d 0d 4d i / o window 1 end-address low byte 80e 0e 4e i / o window 1 end-address high byte 80f 0f 4f memory window 0 start-address low byte 810 10 50 memory window 0 start-address high byte 811 11 51 memory window 0 end-address low byte 812 12 52 memory window 0 end-address high byte 813 13 53 memory window 0 offset-address low byte 814 14 54 memory window 0 offset-address high byte 815 15 55 card detect and general control 816 16 56 reserved 817 17 57 memory window 1 start-address low byte 818 18 58 memory window 1 start-address high byte 819 19 59 memory window 1 end-address low byte 81a 1a 5a memory window 1 end-address high byte 81b 1b 5b memory window 1 offset-address low byte 81c 1c 5c memory window 1 offset-address high byte 81d 1d 5d global control 81e 1e 5e reserved 81f 1f 5f memory window 2 start-address low byte 820 20 60 memory window 2 start-address high byte 821 21 61 memory window 2 end-address low byte 822 22 62 memory window 2 end-address high byte 823 23 63 memory window 2 offset-address low byte 824 24 64 memory window 2 offset-address high byte 825 25 65 reserved 826 26 66 reserved 827 27 67 memory window 3 start-address low byte 828 28 68 memory window 3 start-address high byte 829 29 69 memory window 3 end-address low byte 82a 2a 6a
54 table 51. exca registers and offsets (continued) e x ca register name pci memory address exca offset (hex) e x ca register name offset (hex) card a card b memory window 3 end-address high byte 82b 2b 6b memory window 3 offset-address low byte 82c 2c 6c memory window 3 offset-address high byte 82d 2d 6d reserved 82e 2e 6e reserved 82f 2f 6f memory window 4 start-address low byte 830 30 70 memory window 4 start-address high byte 831 31 71 memory window 4 end-address low byte 832 32 72 memory window 4 end-address high byte 833 33 73 memory window 4 offset-address low byte 834 34 74 memory window 4 offset-address high byte 835 35 75 i/o window 0 offset-address low byte 836 36 76 i/o window 0 offset-address high byte 837 37 77 i/o window 1 offset-address low byte 838 38 78 i/o window 1 offset-address high byte 839 39 79 reserved 83a 3a 7a reserved 83b 3b 7b reserved 83c 3c 7c reserved 83d 3d 7d reserved 83e 3e 7e reserved 83f 3f 7f memory window page 0 840 memory window page 1 841 memory window page 2 842 memory window page 3 843 memory window page 4 844
55 5.1 exca identification and revision register (index 00h) the exca identification and revision register provides host software with information on 16-bit pc card support and intel 82365sl-df compatibility. this register is read-only or read/write, depending on the setting of bit 5 (subsysrw) in the system control register (see section 4.29). see table 52 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca identification and revision type r r r/w r/w r/w r/w r/w r/w default 1 0 0 0 0 1 0 0 register: exca identification and revision type: read-only, read/write offset: cardbus socket address + 800h; card a exca offset 00h card b exca offset 40h default: 84h table 52. exca identification and revision register (index 00h) bit signal type function 76 iftype r interface type. these bits, which are hardwired as 10b, identify the 16-bit pc card support provided by the PCI1420. the PCI1420 supports both i/o and memory 16-bit pc cards. 54 rsvd r/w reserved. bits 5 and 4 can be used for intel 82365sl-df emulation. 30 365rev r/w intel 82365sl-df revision. this field stores the intel 82365sl-df revision supported by the PCI1420. host software can read this field to determine compatibility to the intel 82365sl-df register set. writing 0010b to this field puts the controller in 82365sl mode.
56 5.2 exca interface status register (index 01h) the exca interface status register provides information on the current status of the pc card interface. an x in the default bit value indicates that the value of the bit after reset depends on the state of the pc card interface. see table 53 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca interface status type r r r r r r r r default 0 0 x x x x x x register: exca interface status type: read-only offset: cardbus socket address + 801h; card a exca offset 01h card b exca offset 41h default: 00xx xxxxb table 53. exca interface status register (index 01h) bit signal type function 7 rsvd r reserved. bit 7 returns 0 when read. 6 cardpwr r card power. bit 6 indicates the current power status of the pc card socket. this bit reflects how the exca power control register (see section 5.3) is programmed. bit 6 is encoded as: 0 = v cc and v pp to the socket turned off (default) 1 = v cc and v pp to the socket turned on 5 ready r ready. bit 5 indicates the current status of the ready signal at the pc card interface. 0 = pc card not ready for data transfer 1 = pc card ready for data transfer 4 cardwp r card write protect. bit 4 indicates the current status of wp at the pc card interface. this signal reports to the PCI1420 whether or not the memory card is write protected. furthermore, write protection for an entire PCI1420 16-bit memory window is available by setting the appropriate bit in the memory window offset-address high-byte register. 0 = wp is 0. pc card is read/write. 1 = wp is 1. pc card is read-only. 3 cdetect2 r card detect 2. bit 3 indicates the status of cd2 at the pc card interface. software may use this and bit 2 (cdetect1) to determine if a pc card is fully seated in the socket. 0 = cd2 is 1. no pc card is inserted. 1 = cd2 is 0. pc card is at least partially inserted. 2 cdetect1 r card detect 1. bit 2 indicates the status of cd1 at the pc card interface. software may use this and bit 3 (cdetect2) to determine if a pc card is fully seated in the socket. 0 = cd1 is 1. no pc card is inserted. 1 = cd1 is 0. pc card is at least partially inserted. 10 bvdstat r battery voltage detect. when a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (bvd1, bvd2) at the pc card interface, where bit 1 reflects the bvd2 status and bit 0 reflects bvd1. 00 = battery dead 01 = battery dead 10 = battery low; warning 11 = battery good when a 16-bit i/o card is inserted, this field indicates the status of spkr (bit 1) and stschg (bit 0) at the pc card interface. in this case, the two bits in this field directly reflect the current state of these card outputs.
57 5.3 exca power control register (index 02h) the exca power control register provides pc card power control. bit 7 (coe) of this register controls the 16-bit output enables on the socket interface, and can be used for power management in 16-bit pc card applications. see table 54 and table 55 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca power control type r/w r r r/w r/w r r/w r/w default 0 0 0 0 0 0 0 0 register: exca power control type: read-only, read/write offset: cardbus socket address + 802h; card a exca offset 02h card b exca offset 42h default: 00h table 54. exca power control register 82365sl support (index 02h) bit signal type function 7 coe r/w card output enable. bit 7 controls the state of all of the 16-bit outputs on the PCI1420. this bit is encoded as: 0 = 16-bit pc card outputs disabled (default) 1 = 16-bit pc card outputs enabled 6 rsvd r reserved. bit 6 returns 0 when read. 5 autopwrswen r/w auto power switch enable. 0 = automatic socket power switching based on card detects is disabled. 1 = automatic socket power switching based on card detects is enabled. 4 capwren r/w pc card power enable. 0 = v cc = no connection 1 = v cc is enabled and controlled by bit 2 (excapower) of the system control register (see section 4.29). 32 rsvd r reserved. bits 3 and 2 return 0s when read. 10 excavpp r/w pc card v pp power control. bits 1 and 0 are used to request changes to card v pp . the PCI1420 ignores this field unless v cc to the socket is enabled. this field is encoded as: 00 = no connection (default) 01 = v cc 10 = 12 v 11 = reserved table 55. exca power control register 82365sl-df support (index 02h) bit signal type function 7 coe r/w card output enable. bit 7 controls the state of all of the 16-bit outputs on the PCI1420. this bit is encoded as: 0 = 16-bit pc card outputs disabled (default) 1 = 16-bit pc card outputs enabled 65 rsvd r reserved. bits 6 and 5 return 0s when read. 43 excavcc r/w v cc . bits 4 and 3 are used to request changes to card v cc . this field is encoded as: 00 = 0 v (default) 01 = 0 v reserved 10 = 5 v 11 = 3 v 2 rsvd r reserved. bit 2 returns 0 when read. 10 excavpp r/w v pp . bits 1 and 0 are used to request changes to card v pp . the PCI1420 ignores this field unless v cc to the socket is enabled. this field is encoded as: 00 = no connection (default) 01 = v cc 10 = 12 v 11 = reserved
58 5.4 exca interrupt and general control register (index 03h) the exca interrupt and general control register controls interrupt routing for i/o interrupts, as well as other critical 16-bit pc card functions. see table 56 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca interrupt and general control type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca interrupt and general control type: read/write offset: cardbus socket address + 803h; card a exca offset 03h card b exca offset 43h default: 00h table 56. exca interrupt and general control register (index 03h) bit signal type function 7 ringen r/w card ring indicate enable. bit 7 enables the ring indicate function of bvd1/ri . this bit is encoded as: 0 = ring indicate disabled (default) 1 = ring indicate enabled 6 reset r/w card reset. bit 6 controls the 16-bit pc card reset, and allows host software to force a card reset. bit 6 affects 16-bit cards only. this bit is encoded as: 0 = reset signal asserted (default) 1 = reset signal deasserted 5 cardtype r/w card type. bit 5 indicates the pc card type. this bit is encoded as: 0 = memory pc card installed (default) 1 = i/o pc card installed 4 cscroute r/w pci interrupt csc routing enable bit. when bit 4 is set (high), the card status change interrupts are routed to pci interrupts. when low, the card status change interrupts are routed using bits 74 (cscselect field) in the exca card status change interrupt configuration register (see section 5.6). this bit is encoded as: 0 = csc interrupts are routed by exca registers (default). 1 = csc interrupts are routed to pci interrupts. 30 intselect r/w card interrupt select for i/o pc card functional interrupts. bits 30 select the interrupt routing for i/o pc card functional interrupts. this field is encoded as: 0000 = no interrupt routing (default) . csc interrupts routed to pci interrupts. this bit setting is or'ed with bit 4 (cscroute) for backwards compatibility. 0001 = irq1 enabled 0010 = smi enabled 0011 = irq3 enabled 0100 = irq4 enabled 0101 = irq5 enabled 0100 = irq6 enabled 0111 = irq7 enabled 1000 = irq8 enabled 1001 = irq9 enabled 1010 = irq10 enabled 1011 = irq11 enabled 1100 = irq12 enabled 1101 = irq13 enabled 1110 = irq14 enabled 1111 = irq15 enabled
59 5.5 exca card status-change register (index 04h) the exca card status-change register controls interrupt routing for i/o interrupts as well as other critical 16-bit pc card functions. the register enables these interrupt sources to generate an interrupt to the host. when the interrupt source is disabled, the corresponding bit in this register always reads 0. when an interrupt source is enabled, the corresponding bit in this register is set to indicate that the interrupt source is active. after generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. the interrupt service routine is responsible for resetting the bits in this register as well. resetting a bit is accomplished by one of two methods: a read of this register or an explicit write back of 1 to the status bit. the choice of these two methods is based on bit 2 (interrupt flag clear mode select) in the exca global control register (see section 5.22). see table 57 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca card status-change type r r r r r r r r default 0 0 0 0 0 0 0 0 register: exca card status-change type: read-only offset: cardbus socket address + 804h; card a exca offset 04h card b exca offset 44h default: 00h table 57. exca card status-change register (index 04h) bit signal type function 74 rsvd r reserved. bits 74 return 0s when read. 3 cdchange r card detect change. bit 3 indicates whether a change on cd1 or cd2 occurred at the pc card interface. this bit is encoded as: 0 = no change detected on either cd1 or cd2 1 = change detected on either cd1 or cd2 2 readychange r ready change. when a 16-bit memory is installed in the socket, bit 2 includes whether the source of a PCI1420 interrupt was due to a change on ready at the pc card interface, indicating that the pc card is now ready to accept new data. this bit is encoded as: 0 = no low-to-high transition detected on ready (default) 1 = detected low-to-high transition on ready when a 16-bit i/o card is installed, bit 2 is always 0. 1 batwarn r battery warning change. when a 16-bit memory card is installed in the socket, bit 1 indicates whether the source of a PCI1420 interrupt was due to a battery-low warning condition. this bit is encoded as: 0 = no battery warning condition (default) 1 = detected battery warning condition when a 16-bit i/o card is installed, bit 1 is always 0. 0 batdead r battery dead or status change. when a 16-bit memory card is installed in the socket, bit 0 indicates whether the source of a PCI1420 interrupt was due to a battery dead condition. this bit is encoded as: 0 = stschg deasserted (default) 1 = stschg asserted ring indicate. when the PCI1420 is configured for ring indicate operation, bit 0 indicates the status of ri .
510 5.6 exca card status-change-interrupt configuration register (index 05h) the exca card status-change-interrupt configuration register controls interrupt routing for card status-change interrupts, as well as masking csc interrupt sources. see table 58 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca status-change-interrupt configuration type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca card status-change-interrupt configuration type: read/write offset: cardbus socket address + 805h; card a exca offset 05h card b exca offset 45h default: 00h table 58. exca card status-change-interrupt configuration register (index 05h) bit signal type function 74 cscselect r/w interrupt select for card status change. bits 74 select the interrupt routing for card status change interrupts. 0000 = csc interrupts routed to pci interrupts if bit 5 (csc) of the diagnostic register is set to 1 (see section 4.34). in this case bit 4 (cscroute) of the exca interrupt and general control register is a adon't careo (see section 5.4). this is the default setting. 0000 = no isa interrupt routing if bit 5 (csc) of the diagnostic register is set to 0 (see section 4.34). in this case, csc interrupts are routed to pci interrupts by setting bit 4 (cscroute) of the exca interrupt and general control register to 1 (see section 5.4). this field is encoded as: 0000 = no interrupt routing (default) 1000 = irq8 enabled 0001 = irq1 enabled 1001 = irq9 enabled 0010 = smi enabled 1010 = irq10 enabled 0011 = irq3 enabled 1011 = irq11 enabled 0100 = irq4 enabled 1100 = irq12 enabled 0101 = irq5 enabled 1101 = irq13 enabled 0110 = irq6 enabled 1110 = irq14 enabled 0111 = irq7 enabled 1111 = irq15 enabled 3 cden r/w card detect enable. bit 3 enables interrupts on cd1 or cd2 changes. this bit is encoded as: 0 = disables interrupts on cd1 or cd2 line changes (default) 1 = enables interrupts on cd1 or cd2 line changes 2 readyen r/w ready enable. bit 2 enables/disables a low-to-high transition on pc card ready to generate a host interrupt. this interrupt source is considered a card status change. this bit is encoded as: 0 = disables host interrupt generation (default) 1 = enables host interrupt generation 1 batwarnen r/w battery warning enable. bit 1 enables/disables a battery warning condition to generate a csc interrupt. this bit is encoded as: 0 = disables host interrupt generation (default) 1 = enables host interrupt generation 0 batdeaden r/w battery dead enable. bit 0 enables/disables a battery dead condition on a memory pc card or assertion of the stschg i/o pc card signal to generate a csc interrupt. 0 = disables host interrupt generation (default) 1 = enables host interrupt generation
511 5.7 exca address window enable register (index 06h) the exca address window enable register enables/disables the memory and i/o windows to the 16-bit pc card. by default, all windows to the card are disabled. the PCI1420 does not acknowledge pci memory or i/o cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or i/o window start/end/offset address registers. see table 59 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca address window enable type r/w r/w r r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca address window enable type: read-only, read/write offset: cardbus socket address + 806h; card a exca offset 06h card b exca offset 46h default: 00h table 59. exca address window enable register (index 06h) bit signal type function 7 iowin1en r/w i/o window 1 enable. bit 7 enables/disables i/o window 1 for the pc card. this bit is encoded as: 0 = i/o window 1 disabled (default) 1 = i/o window 1 enabled 6 iowin0en r/w i/o window 0 enable. bit 6 enables/disables i/o window 0 for the pc card. this bit is encoded as: 0 = i/o window 0 disabled (default) 1 = i/o window 0 enabled 5 rsvd r reserved. bit 5 returns 0 when read. 4 memwin4en r/w memory window 4 enable. bit 4 enables/disables memory window 4 for the pc card. this bit is encoded as: 0 = memory window 4 disabled (default) 1 = memory window 4 enabled 3 memwin3en r/w memory window 3 enable. bit 3 enables/disables memory window 3 for the pc card. this bit is encoded as: 0 = memory window 3 disabled (default) 1 = memory window 3 enabled 2 memwin2en r/w memory window 2 enable. bit 2 enables/disables memory window 2 for the pc card. this bit is encoded as: 0 = memory window 2 disabled (default) 1 = memory window 2 enabled 1 memwin1en r/w memory window 1 enable. bit 1 enables/disables memory window 1 for the pc card. this bit is encoded as: 0 = memory window 1 disabled (default) 1 = memory window 1 enabled 0 memwin0en r/w memory window 0 enable. bit 0 enables/disables memory window 0 for the pc card. this bit is encoded as: 0 = memory window 0 disabled (default) 1 = memory window 0 enabled
512 5.8 exca i/o window control register (index 07h) the exca i/o window control register contains parameters related to i/o window sizing and cycle timing. see table 510 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca i/o window control type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i /o window control type: read/write offset: cardbus socket address + 807h; card a exca offset 07h card b exca offset 47h default: 00h table 510. exca i /o window control register (index 07h) bit signal type function 7 waitstate1 r/w i/o window 1 wait state. bit 7 controls the i/o window 1 wait state for 16-bit i/o accesses. bit 7 has no effect on 8-bit accesses. this wait-state timing emulates the isa wait state used by the intel 82365sl-df. this bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent isa wait state. 6 zerows1 r/w i/o window 1 zero wait state. bit 6 controls the i/o window 1 wait state for 8-bit i/o accesses. bit 6 has no effect on 16-bit accesses. this wait-state timing emulates the isa wait state used by the intel 82365sl-df. this bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three isa cycles. 5 iosis16w1 r/w i/o window 1 iois16 source. bit 5 controls the i/o window 1 automatic data sizing feature that uses iois16 from the pc card to determine the data width of the i/o data transfer. this bit is encoded as: 0 = window data width determined by datasize1, bit 4 (default). 1 = window data width determined by iois16 . 4 datasize1 r/w i/o window 1 data size. bit 4 controls the i/o window 1 data size. bit 4 is ignored if bit 5 (iosis16w1) is set. this bit is encoded as: 0 = window data width is 8 bits (default). 1 = window data width is 16 bits. 3 waitstate0 r/w i/o window 0 wait state. bit 3 controls the i/o window 0 wait state for 16-bit i/o accesses. bit 3 has no effect on 8-bit accesses. this wait-state timing emulates the isa wait state used by the intel 82365sl-df. this bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent isa wait state. 2 zerows0 r/w i/o window 0 zero wait state. bit 2 controls the i/o window 0 wait state for 8-bit i/o accesses. bit 2 has no effect on 16-bit accesses. this wait-state timing emulates the isa wait state used by the intel 82365sl-df. this bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three isa cycles. 1 iosis16w0 r/w i/o window 0 iois16 source. bit 1 controls the i/o window 0 automatic data sizing feature that uses iois16 from the pc card to determine the data width of the i/o data transfer. this bit is encoded as: 0 = window data width is determined by datasize0, bit 0 (default). 1 = window data width is determined by iois16 . 0 datasize0 r/w i/o window 0 data size. bit 0 controls the i/o window 0 data size. bit 0 is ignored if bit 1 (iosis16w0) is set. this bit is encoded as: 0 = window data width is 8 bits (default). 1 = window data width is 16 bits.
513 5.9 exca i/o windows 0 and 1 start-address low-byte registers (index 08h, 0ch) these registers contain the low byte of the 16-bit i/o window start address for i/o windows 0 and 1. the 8 bits of these registers correspond to the lower 8 bits of the start address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 start-address low byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 start-address low byte offset: cardbus socket address + 808h; card a exca offset 08h card b exca offset 48h register: exca i/o window 1 start-address low byte offset: cardbus socket address + 80ch; card a exca offset 0ch card b exca offset 4ch type: read/write default: 00h size: one byte 5.10 exca i/o windows 0 and 1 start-address high-byte registers (index 09h, 0dh) these registers contain the high byte of the 16-bit i/o window start address for i/o windows 0 and 1. the 8 bits of these registers correspond to the upper 8 bits of the end address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 start-address high byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 start-address high byte offset: cardbus socket address + 809h; card a exca offset 09h card b exca offset 49h register: exca i/o window 1 start-address high byte offset: cardbus socket address + 80dh; card a exca offset 0dh card b exca offset 4dh type: read/write default: 00h size: one byte
514 5.11 exca i/o windows 0 and 1 end-address low-byte registers (index 0ah, 0eh) these registers contain the low byte of the 16-bit i/o window end address for i/o windows 0 and 1. the 8 bits of these registers correspond to the lower 8 bits of the end address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 end-address low byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i /o window 0 end-address low byte offset: cardbus socket address + 80ah; card a exca offset 0ah card b exca offset 4ah register: exca i /o window 1 end-address low byte offset: cardbus socket address + 80eh; card a exca offset 0eh card b exca offset 4eh type: read/write default: 00h size: one byte 5.12 exca i/o windows 0 and 1 end-address high-byte registers (index 0bh, 0fh) these registers contain the high byte of the 16-bit i/o window end address for i/o windows 0 and 1. the 8 bits of these registers correspond to the upper 8 bits of the end address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 end-address high byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i /o window 0 end-address high byte offset: cardbus socket address + 80bh; card a exca offset 0bh card b exca offset 4bh register: exca i /o window 1 end-address high byte offset: cardbus socket address + 80fh; card a exca offset 0fh card b exca offset 4fh type: read/write default: 00h size: one byte
515 5.13 exca memory windows 04 start-address low-byte registers (index 10h, 18h, 20h, 28h, 30h) these registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. the 8 bits of these registers correspond to bits a19a12 of the start address. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 start-address low byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 start-address low byte offset: cardbus socket address + 810h; card a exca offset 10h card b exca offset 50h register: exca memory window 1 start-address low byte offset: cardbus socket address + 818h; card a exca offset 18h card b exca offset 58h register: exca memory window 2 start-address low byte offset: cardbus socket address + 820h; card a exca offset 20h card b exca offset 60h register: exca memory window 3 start-address low byte offset: cardbus socket address + 828h; card a exca offset 28h card b exca offset 68h register: exca memory window 4 start-address low byte offset: cardbus socket address + 830h; card a exca offset 30h card b exca offset 70h type: read/write default: 00h size: one byte
516 5.14 exca memory windows 04 start-address high-byte registers (index 11h, 19h, 21h, 29h, 31h) these registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. the lower 4 bits of these registers correspond to bits a23a20 of the start address. in addition, the memory window data width and wait states are set in this register. see table 511 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 start-address high byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 start-address high byte offset: cardbus socket address + 811h; card a exca offset 11h card b exca offset 51h register: exca memory window 1 start-address high byte offset: cardbus socket address + 819h; card a exca offset 19h card b exca offset 59h register: exca memory window 2 start-address high byte offset: cardbus socket address + 821h; card a exca offset 21h card b exca offset 61h register: exca memory window 3 start-address high byte offset: cardbus socket address + 829h; card a exca offset 29h card b exca offset 69h register: exca memory window 4 start-address high byte offset: cardbus socket address + 831h; card a exca offset 31h card b exca offset 71h type: read/write default: 00h size: one byte table 511. exca memory windows 04 start-address high-byte registers (index 11h, 19h, 21h, 29h, 31h) bit signal type function 7 datasize r/w data size. bit 7 controls the memory window data width. this bit is encoded as: 0 = window data width is 8 bits (default). 1 = window data width is 16 bits. 6 zerowait r/w zero wait state. bit 6 controls the memory window wait state for 8- and 16-bit accesses. this wait-state timing emulates the isa wait state used by the intel 82365sl-df. this bit is encoded as: 0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three isa cycles. 16-bit cycles are reduced to equivalent of two isa cycles. 54 scratch r/w scratch pad bits. bits 5 and 4 have no effect on memory window operation. 30 stahn r/w start-address high nibble. bits 30 represent the upper address bits a23a20 of the memory window start address.
517 5.15 exca memory windows 04 end-address low-byte registers (index 12h, 1ah, 22h, 2ah, 32h) these registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. the 8 bits of these registers correspond to bits a19a12 of the end address. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 end-address low byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 end-address low byte offset: cardbus socket address + 812h; card a exca offset 12h card b exca offset 52h register: exca memory window 1 end-address low byte offset: cardbus socket address + 81ah; card a exca offset 1ah card b exca offset 5ah register: exca memory window 2 end-address low byte offset: cardbus socket address + 822h; card a exca offset 22h card b exca offset 62h register: exca memory window 3 end-address low byte offset: cardbus socket address + 82ah; card a exca offset 2ah card b exca offset 6ah register: exca memory window 4 end-address low byte offset: cardbus socket address + 832h; card a exca offset 32h card b exca offset 72h type: read/write default: 00h size: one byte
518 5.16 exca memory windows 04 end-address high-byte registers (index 13h, 1bh, 23h, 2bh, 33h) these registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. the lower 4 bits of these registers correspond to bits a23a20 of the end address. in addition, the memory window wait states are set in this register. see table 512 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 end-address high byte type r/w r/w r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 end-address high byte offset: cardbus socket address + 813h; card a exca offset 13h card b exca offset 53h register: exca memory window 1 end-address high byte offset: cardbus socket address + 81bh; card a exca offset 1bh card b exca offset 5bh register: exca memory window 2 end-address high byte offset: cardbus socket address + 823h; card a exca offset 23h card b exca offset 63h register: exca memory window 3 end-address high byte offset: cardbus socket address + 82bh; card a exca offset 2bh card b exca offset 6bh register: exca memory window 4 end-address high byte offset: cardbus socket address + 833h; card a exca offset 33h card b exca offset 73h type: read-only, read/write default: 00h size: one byte table 512. exca memory windows 04 end-address high-byte registers (index 13h, 1bh, 23h, 2bh, 33h) bit signal type function 76 memws r/w wait state. bits 7 and 6 specify the number of equivalent isa wait states to be added to 16-bit memory accesses. the number of wait states added is equal to the binary value of these two bits. 54 rsvd r reserved. bits 5 and 4 return 0s when read. 30 endhn r/w end-address high nibble. bits 30 represent the upper address bits a23a20 of the memory window end address.
519 5.17 exca memory windows 04 offset-address low-byte registers (index 14h, 1ch, 24h, 2ch, 34h) these registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. the 8 bits of these registers correspond to bits a19a12 of the offset address. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 offset-address low byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 offset-address low byte offset: cardbus socket address + 814h; card a exca offset 14h card b exca offset 54h register: exca memory window 1 offset-address low byte offset: cardbus socket address + 81ch; card a exca offset 1ch card b exca offset 5ch register: exca memory window 2 offset-address low byte offset: cardbus socket address + 824h; card a exca offset 24h card b exca offset 64h register: exca memory window 3 offset-address low byte offset: cardbus socket address + 82ch; card a exca offset 2ch card b exca offset 6ch register: exca memory window 4 offset-address low byte offset: cardbus socket address + 834h; card a exca offset 34h card b exca offset 74h type: read/write default: 00h size: one byte
520 5.18 exca memory windows 04 offset-address high-byte registers (index 15h, 1dh, 25h, 2dh, 35h) these registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. the lower 6 bits of these registers correspond to bits a25a20 of the offset address. in addition, the write protection and common/attribute memory configurations are set in this register. see table 513 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 offset-address high byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 offset-address high byte offset: cardbus socket address + 815h; card a exca offset 15h card b exca offset 55h register: exca memory window 1 offset-address high byte offset: cardbus socket address + 81dh; card a exca offset 1dh card b exca offset 5dh register: exca memory window 2 offset-address high byte offset: cardbus socket address + 825h; card a exca offset 25h card b exca offset 65h register: exca memory window 3 offset-address high byte offset: cardbus socket address + 82dh; card a exca offset 2dh card b exca offset 6dh register: exca memory window 4 offset-address high byte offset: cardbus socket address + 835h; card a exca offset 35h card b exca offset 75h type: read/write default: 00h size: one byte table 513. exca memory windows 04 offset-address high-byte registers (index 15h, 1dh, 25h, 2dh, 35h) bit signal type function 7 winwp r/w write protect. bit 7 specifies whether write operations to this memory window are enabled. this bit is encoded as: 0 = write operations are allowed (default). 1 = write operations are not allowed. 6 reg r/w bit 6 specifies whether this memory window is mapped to card attribute or common memory. this bit is encoded as: 0 = memory window is mapped to common memory (default). 1 = memory window is mapped to attribute memory. 50 offhb r/w offset-address high byte. bits 50 represent the upper address bits a25a20 of the memory window offset address.
521 5.19 exca i/o windows 0 and 1 offset-address low-byte registers (index 36h, 38h) these registers contain the low byte of the 16-bit i/o window offset address for i/o windows 0 and 1. the 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 offset-address low byte type r/w r/w r/w r/w r/w r/w r/w r default 0 0 0 0 0 0 0 0 register: exca i/o window 0 offset-address low byte offset: cardbus socket address + 836h; card a exca offset 36h card b exca offset 76h register: exca i/o window 1 offset-address low byte offset: cardbus socket address + 838h; card a exca offset 38h card b exca offset 78h type: read-only, read/write default: 00h size: one byte 5.20 exca i/o windows 0 and 1 offset-address high-byte registers (index 37h, 39h) these registers contain the high byte of the 16-bit i/o window offset address for i/o windows 0 and 1. the 8 bits of these registers correspond to the upper 8 bits of the offset address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 offset-address high byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 offset-address high byte offset: cardbus socket address + 837h; card a exca offset 37h card b exca offset 77h register: exca i/o window 1 offset-address high byte offset: cardbus socket address + 839h; card a exca offset 39h card b exca offset 79h type: read/write default: 00h size: one byte
522 5.21 exca card detect and general control register (index 16h) the exca card detect and general control register controls how the exca registers for the socket respond to card removal, as well as reports the status of vs1 and vs2 at the pc card interface. see table 514 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca i/o card detect and general control type r r r/w r/w r r r/w r default x x 0 0 0 0 0 0 register: exca card detect and general control type: read-only, read/write offset: cardbus socket address + 816h; card a exca offset 16h card b exca offset 56h default: xx00 0000b table 514. exca card detect and general control register (index 16h) bit signal type function 7 vs2stat r vs2 state. bit 7 reports the current state of vs2 at the pc card interface and, therefore, does not have a default value. 0 = vs2 low 1 = vs2 high 6 vs1stat r vs1 state. bit 6 reports the current state of vs1 at the pc card interface and, therefore, does not have a default value. 0 = vs1 low 1 = vs1 high 5 swcsc r/w software card detect interrupt. if bit 3 (cden) in the exca card status-change-interrupt configuration register is set (see section 5.6), then writing a 1 to bit 5 causes a card-detect card-status change interrupt for the associated card socket. if bit 3 (cden) in the exca card status-change-interrupt configuration register is cleared to 0 (see section 5.6), then writing a 1 to bit 5 has no effect. a read operation of this bit always returns 0. 4 cdresume r/w card detect resume enable. if bit 4 is set to 1, then once a card detect change has been detected on cd1 and cd2 inputs, ri_out goes from high to low. ri_out remains low until bit 0 (card status change) in the exca card status-change register is cleared (see section 5.5). if this bit is a 0, then the card detect resume functionality is disabled. 0 = card detect resume disabled (default) 1 = card detect resume enabled 32 rsvd r reserved. bits 3 and 2 return 0s when read. 1 regconfig r/w register configuration on card removal. bit 1 controls how the exca registers for the socket react to a card removal event. this bit is encoded as: 0 = no change to exca registers on card removal (default) 1 = reset exca registers on card removal 0 rsvd r reserved. bit 0 returns 0 when read.
523 5.22 exca global control register (index 1eh) the exca global control register controls both pc card sockets and is not duplicated for each socket. the host interrupt mode bits in this register are retained for intel 82365sl-df compatibility. see table 515 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca global control type r r r r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca global control type: read-only, read/write offset: cardbus socket address + 81eh; card a exca offset 1eh card b exca offset 5eh default: 00h table 515. exca global control register (index 1eh) bit signal type function 75 rsvd r reserved. bits 75 return 0s when read. 4 intmodeb r/w level/edge interrupt mode select card b. bit 4 selects the signaling mode for the PCI1420 host interrupt for card b interrupts. this bit is encoded as: 0 = host interrupt is edge mode (default). 1 = host interrupt is level mode. 3 intmodea r/w level/edge interrupt mode select card a. bit 3 selects the signaling mode for the PCI1420 host interrupt for card a interrupts. this bit is encoded as: 0 = host interrupt is edge mode (default). 1 = host interrupt is level mode. 2 ifcmode r/w interrupt flag clear mode select. bit 2 selects the interrupt flag clear mechanism for the flags in the exca card status change register (see section 5.5). this bit is encoded as: 0 = interrupt flags are cleared by read of csc register (default). 1 = interrupt flags are cleared by explicit write back of 1. 1 cscmode r/w card status change level/edge mode select. bit 1 selects the signaling mode for the PCI1420 host interrupt for card status changes. this bit is encoded as: 0 = host interrupt is edge mode (default). 1 = host interrupt is level mode. 0 pwrdwn r/w power-down mode select. when bit 0 is set to 1, the PCI1420 is in power-down mode. in power-down mode, the PCI1420 card outputs are high impedance until an active cycle is executed on the card interface. following an active cycle, the outputs are again high impedance. the PCI1420 still receives dma requests, functional interrupts, and/or card status change interrupts; however, an actual card access is required to wake up the interface. this bit is encoded as: 0 = power-down mode is disabled (default). 1 = power-down mode is enabled.
524 5.23 exca memory windows 04 page register the upper 8 bits of a 4-byte pci memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. each window has its own page register, all of which default to 00h. by programming this register to a nonzero value, host software can locate 16-bit memory windows in any 1 of 256 16m-byte regions in the 4g-byte pci address space. these registers are only accessible when the exca registers are memory mapped, that is, these registers cannot be accessed using the index/data i/o scheme. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 page type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory windows 04 page type: read/write offset: cardbus socket address + 840h, 841h, 842h, 843h, 844h default: 00h
61 6 cardbus socket registers (functions 0 and 1) the 1997 pc card standard requires a cardbus socket controller to provide five 32-bit registers that report and control socket-specific functions. the PCI1420 provides the cardbus socket/exca base address register (see section 4.12) to locate these cardbus socket registers in pci memory address space. each socket has a separate base address register for accessing the cardbus socket registers (see figure 61). table 61 gives the location of the socket registers in relation to the cardbus socket/exca base address. the PCI1420 implements an additional register at offset 20h that provides power management control for the socket. cardbus socket/exca base address 16-bit legacy-mode base address 10h 44h note: the cardbus socket/exca base address mode register is separate for functions 0 and 1. PCI1420 configuration registers cardbus socket a registers host memory space 00h exca registers card a 20h 800h 844h offset cardbus socket b registers host memory space 00h exca registers card b 20h 800h 844h offset offset figure 61. accessing cardbus socket registers through pci memory table 61. cardbus socket registers register name offset socket event 00h socket mask 04h socket present state 08h socket force event 0ch socket control 10h reserved 14h reserved 18h reserved 1ch socket power management 20h
62 6.1 socket event register the socket event register indicates a change in socket status has occurred. these bits do not indicate what the change is, only that one has occurred. software must read the socket present state register (see section 6.3) for current status. each bit in this register can be cleared by writing a 1 to that bit. the bits in this register can be set to a 1 by software by writing a 1 to the corresponding bit in the socket force event register (see section 6.4). all bits in this register are cleared by pci reset. they can be immediately set again, if, when coming out of pc card reset, the bridge finds the status unchanged (that is, cstschg reasserted or card detect is still true). software must clear this register before enabling interrupts. if it is not cleared when interrupts are enabled, then an interrupt is generated (but not masked) based on any bit set. see table 62 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket event type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket event type r r r r r r r r r r r r r/c r/c r/c r/c default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket event type: read-only, read/write, read/write to clear offset: cardbus socket address + 00h default: 0000 0000h table 62. socket event register bit signal type function 314 rsvd r reserved. bits 314 return 0s when read. 3 pwrevent r/c power cycle. bit 3 is set when the PCI1420 detects that bit 3 (pwrcycle) in the socket present state register (see section 6.3) has changed state. this bit is cleared by writing a 1. 2 cd2event r/c ccd2 . bit 2 is set when the PCI1420 detects that bit 2 (cdetect2) in the socket present state register (see section 6.3) has changed state. this bit is cleared by writing a 1. 1 cd1event r/c ccd1 . bit 3 is set when the PCI1420 detects that bit 1 (cdetect1) in the socket present state register (see section 6.3) has changed state. this bit is cleared by writing a 1. 0 cstsevent r/c cstschg . bit 0 is set when bit 0 (cardsts) in the socket present state register (see section 6.3) has changed state. for cardbus cards, bit 0 is set on the rising edge of cstschg . for 16-bit pc cards, bit 0 is set on both transitions of cstschg . this bit is reset by writing a 1.
63 6.2 socket mask register the socket mask register allows software to control the cardbus card events that generate a status change interrupt. the state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (see section 6.1). see table 63 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket mask type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket mask type r r r r r r r r r r r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket mask type: read-only, read/write offset: cardbus socket address + 04h default: 0000 0000h table 63. socket mask register bit signal type function 314 rsvd r reserved. bits 314 return 0s when read. 3 pwrmask r/w power cycle. bit 3 masks bit 3 (pwrcycle) in the socket present state register (see section 6.3) from causing a status change interrupt. 0 = pwrcycle event does not cause csc interrupt (default). 1 = pwrcycle event causes csc interrupt. 21 cdmask r/w card detect mask. bits 2 and 1 mask bits 1 and 2 (cdetect1 and cdetect2) in the socket present state register (see section 6.3) from causing a csc interrupt. 00 = insertion/removal does not cause csc interrupt (default). 01 = reserved (undefined) 10 = reserved (undefined) 11 = insertion/removal causes csc interrupt. 0 cstsmask r/w cstschg mask. bit 0 masks bit 0 (cardsts) in the socket present state register (see section 6.3) from causing a csc interrupt. 0 = cardsts event does not cause csc interrupt (default). 1 = cardsts event causes csc interrupt.
64 6.3 socket present state register the socket present state register reports information about the socket interface. write transactions to the socket force event register (see section 6.4) are reflected here, as well as general socket interface status. information about pc card v cc support and card type is only updated at each insertion. also note that the PCI1420 uses ccd1 and ccd2 during card identification, and changes on these signals during this operation are not reflected in this register. see table 64 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket present state type r r r r r r r r r r r r r r r r default 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket present state type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 x 0 0 0 x x x register: socket present state type: read-only offset: cardbus socket address + 08h default: 3000 00xxh table 64. socket present state register bit signal type function 31 yvsocket r yv socket. bit 31 indicates whether or not the socket can supply v cc = y.y v to pc cards. the PCI1420 does not support y.y-v v cc ; therefore, this bit is always reset unless overridden by the socket force event register (see section 6.4). this bit is hardwired to 0. 30 xvsocket r xv socket. bit 30 indicates whether or not the socket can supply v cc = x.x v to pc cards. the PCI1420 does not support x.x-v v cc ; therefore, this bit is always reset unless overridden by the socket force event register (see section 6.4). this bit is hardwired to 0. 29 3vsocket r 3-v socket. bit 29 indicates whether or not the socket can supply v cc = 3.3 v to pc cards. the PCI1420 does support 3.3-v v cc ; therefore, this bit is always set unless overridden by the socket force event register (see section 6.4). 28 5vsocket r 5-v socket. bit 28 indicates whether or not the socket can supply v cc = 5 v to pc cards. the PCI1420 does support 5-v v cc ; therefore, this bit is always set unless overridden by the socket force event register (see section 6.4). 2714 rsvd r reserved. bits 2714 return 0s when read. 13 yvcard r yv card. bit 13 indicates whether or not the pc card inserted in the socket supports v cc = y.y v. 12 xvcard r xv card. bit 12 indicates whether or not the pc card inserted in the socket supports v cc = x.x v. 11 3vcard r 3-v card. bit 11 indicates whether or not the pc card inserted in the socket supports v cc = 3.3 v. 10 5vcard r 5-v card. bit 10 indicates whether or not the pc card inserted in the socket supports v cc = 5 v. 9 badvccreq r bad v cc request. bit 9 indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = normal operation (default) 1 = invalid v cc request by host software 8 datalost r data lost. bit 8 indicates that a pc card removal event may have caused lost data because the cycle did not terminate properly or because write data still resides in the PCI1420. 0 = normal operation (default) 1 = potential data loss due to card removal 7 notacard r not a card. bit 7 indicates that an unrecognizable pc card has been inserted in the socket. this bit is not updated until a valid pc card is inserted into the socket. 0 = normal operation (default) 1 = unrecognizable pc card detected
65 table 64. socket present state register (continued) bit signal type function 6 ireqcint r ready(ireq )//cint . bit 6 indicates the current status of ready(ireq )//cint at the pc card interface. 0 = ready(ireq )//cint low 1 = ready(ireq )//cint high 5 cbcard r cardbus card detected. bit 5 indicates that a cardbus pc card is inserted in the socket. this bit is not updated until another card interrogation sequence occurs (card insertion). 4 16bitcard r 16-bit card detected. bit 4 indicates that a 16-bit pc card is inserted in the socket. this bit is not updated until another card interrogation sequence occurs (card insertion). 3 pwrcycle r power cycle. bit 3 indicates that the status of each card powering request. this bit is encoded as: 0 = socket powered down (default) 1 = socket powered up 2 cdetect2 r ccd2 . bit 2 reflects the current status of ccd2 at the pc card interface. changes to this signal during card interrogation are not reflected here. 0 = ccd2 low (pc card may be present) 1 = ccd2 high (pc card not present) 1 cdetect1 r ccd1 . bit 1 reflects the current status of ccd1 at the pc card interface. changes to this signal during card interrogation are not reflected here. 0 = ccd1 low (pc card may be present) 1 = ccd1 high (pc card not present) 0 cardsts r cstschg . bit 0 reflects the current status of cstschg at the pc card interface. 0 = cstschg low 1 = cstschg high
66 6.4 socket force event register the socket force event register is used to force changes to the socket event register (see section 6.1) and the socket present state register (see section 6.3). bit 14 (cvstest) in this register must be written when forcing changes that require card interrogation. see table 65 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket force event type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket force event type r w w w w w w w w r w w w w w w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket force event type: read-only, write-only offset: cardbus socket address + 0ch default: 0000 0000h table 65. socket force event register bit signal type function 3115 rsvd r reserved. bits 3115 return 0s when read. 14 cvstest w card vs test. when bit 14 is set, the PCI1420 re-interrogates the pc card, updates the socket present state register (see section 6.3), and enables the socket control register (see section 6.5). 13 fyvcard w force yv card. write transactions to bit 13 cause bit 13 (yvcard) in the socket present state register to be written (see section 6.3). when set, this bit disables the socket control register (see section 6.5). 12 fxvcard w force xv card. write transactions to bit 12 cause bit 12 (xvcard) in the socket present state register to be written (see section 6.3). when set, this bit disables the socket control register (see section 6.5). 11 f3vcard w force 3-v card. write transactions to bit 11 cause bit 11 (3vcard) in the socket present state register to be written (see section 6.3). when set, this bit disables the socket control register (see section 6.5). 10 f5vcard w force 5-v card. write transactions to bit 10 cause bit 10 (5vcard) in the socket present state register to be written (see section 6.3). when set, this bit disables the socket control register (see section 6.5). 9 fbadvccreq w force bad v cc request. changes to bit 9 (badvccreq) in the socket present state register (see section 6.3) can be made by writing to bit 9. 8 fdatalost w force data lost. write transactions to bit 8 cause bit 8 (datalost) in the socket present state register to be written (see section 6.3). 7 fnotacard w force not a card. write transactions to bit 7 cause bit 7 (notacard) in the socket present state register to be written (see section 6.3). 6 rsvd r reserved. bit 6 returns 0 when read. 5 fcbcard w force cardbus card. write transactions to bit 5 cause bit 5 (cbcard) in the socket present state register to be written (see section 6.3). 4 f16bitcard w force 16-bit card. write transactions to bit 4 cause bit 4 (16bitcard) in the socket present state register to be written (see section 6.3). 3 fpwrcycle w force power cycle. write transactions to bit 3 cause bit 3 (pwrevent) in the socket event register to be written (see section 6.1), and bit 3 (pwrcycle) in the socket present state register is unaffected (see section 6.3). 2 fcdetect2 w force ccd2 . write transactions to bit 2 cause bit 2 (cd2event) in the socket event register to be written (see section 6.1), and bit 2 (cdetect2) in the socket present state register is unaffected (see section 6.3). 1 fcdetect1 w force ccd1 . write transactions to bit 1 cause bit 1 (cd1event) in the socket event register to be written (see section 6.1), and bit 1 (cdetect1) in the socket present state register is unaffected (see section 6.3). 0 fcardsts w force cstschg. write transactions to bit 0 cause bit 0 (cstsevent) in the socket event register to be written (see section 6.1), and bit 0 (cardsts) in the socket present state register is unaffected (see section 6.3).
67 6.5 socket control register the socket control register provides control of the voltages applied to the socket and instructions for cb clkrun protocol. the PCI1420 ensures that the socket is powered up only at acceptable voltages when a cardbus card is inserted. see table 66 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket control type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket control type r r r r r r r r r/w r/w r/w r/w r r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket control type: read-only, read/write offset: cardbus socket address + 10h default: 0000 0000h table 66. socket control register bit signal type function 318 rsvd r reserved. bits 318 return 0s when read. 7 stopclk r/w cb clkrun protocol instructions. 0 = cb clkrun protocol can only attempt to stop/slow the cb clock if the socket is idle and the pci clkrun protocol is preparing to stop/slow the pci bus clock. 1 = cb clkrun protocol can attempt to stop/slow the cb clock if the socket is idle. 64 vccctrl r/w v cc control. bits 64 request card v cc changes. 000 = request power off (default) 100 = request v cc = x.x v 001 = reserved 101 = request v cc = y.y v 010 = request v cc = 5 v 110 = reserved 011 = request v cc = 3.3 v 111 = reserved 3 rsvd r reserved. bit 3 returns 0 when read. 20 vppctrl r/w v pp control. bits 20 request card v pp changes. 000 = request power off (default) 100 = request v pp = x.x v 001 = request v pp = 12 v 101 = request v pp = y.y v 010 = request v pp = 5 v 110 = reserved 011 = request v pp = 3.3 v 111 = reserved
68 6.6 socket power management register this register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. see table 67 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket power management type r r r r r r r r r r r r r r r r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket power management type r r r r r r r r r r r r r r r r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket power management type: read-only, read/write offset: cardbus socket address + 20h default: 0000 0000h table 67. socket power management register bit signal type function 3126 rsvd r reserved. bits 3126 return 0s when read. 25 sktacces r socket access status. this bit provides information on when a socket access has occurred. this bit is cleared by a read access. 0 = a pc card access has not occurred (default). 1 = a pc card access has occurred. 24 sktmode r socket mode status. this bit provides clock mode information. 0 = clock is operating normally. 1 = clock frequency has changed. 2317 rsvd r reserved. bits 2317 return 0s when read. 16 clkctrlen r/w cardbus clock control enable. when bit 16 is set, bit 0 (clkctrl) is enabled. 0 = clock control is disabled (default). 1 = clock control is enabled. 151 rsvd r reserved. bits 151 return 0s when read. 0 clkctrl r/w cardbus clock control. this bit determines whether the cb clkrun protocol stops or slows the cb clock during idle states. bit 16 (clkctrlen) enables this bit. 0 = allows cb clkrun protocol to stop the cb clock (default). 1 = allows cb clkrun protocol to slow the cb clock by a factor of 16.
71 7 distributed dma (ddma) registers the dma base address, programmable in pci configuration space at offset 98h, points to a 16-byte region in pci i/o space where the ddma registers reside. the names and locations of these registers are summarized in table 71. these PCI1420 register definitions are identical in function, but differ in location, to the 8237 dma controller. the similarity between the register models retains some level of compatibility with legacy dma and simplifies the translation required by the master dma device when it forwards legacy dma writes to dma channels. while the dma register definitions are identical to those in the 8237 of the same name, some register bits defined in the 8237 do not apply to distributed dma in a pci environment. in such cases, the PCI1420 implements these obsolete register bits as read-only nonfunctional bits. the reserved registers shown in table 71 are implemented as read-only and return 0s when read. write transactions to reserved registers have no effect. table 71. distributed dma registers type register name dma base address offset r reserved page current address 00h w reser v ed page base address r reserved reserved current count 04h w reser v ed reser v ed base count r n/a reserved n/a status 08h w mode reser v ed request command r multichannel reserved n/a reserved 0ch w mask reser v ed master clear reser v ed 7.1 dma current address/base address register the dma current address/base address register sets the starting (base) memory address of a dma transfer. read transactions from this register indicate the current memory address of a direct memory transfer. for the 8-bit dma transfer mode, the current address register contents are presented on ad15ad0 of the pci bus during the address phase. bits 70 of the dma page register (see section 7.2) are presented on ad23ad16 of the pci bus during the address phase. for the 16-bit dma transfer mode, the current address register contents are presented on ad16ad1 of the pci bus during the address phase, and ad0 is driven to logic 0. bits 71 of the dma page register (see section 7.2) are presented on ad23ad17 of the pci bus during the address phase, and bit 0 is ignored. bit 15 14 13 12 11 10 9 8 name dma current address/base address type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name dma current address/base address type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: dma current address/base address type: read/write offset: dma base address + 00h default: 0000h size: two bytes
72 7.2 dma page register the dma page register sets the upper byte of the address of a dma transfer. details of the address represented by this register are explained in section 7.1, dma current address/base address register . bit 7 6 5 4 3 2 1 0 name dma page type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: dma page type: read/write offset: dma base address + 02h default: 00h size: one byte 7.3 dma current count/base count register the dma current count/base count register sets the total transfer count, in bytes, of a direct memory transfer. read transactions to this register indicate the current count of a direct memory transfer. in the 8-bit transfer mode, the count is decremented by 1 after each transfer, and the count is decremented by 2 after each transfer in the 16-bit transfer mode. bit 15 14 13 12 11 10 9 8 name dma current count/base count type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name dma current count/base count type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: dma current count/base count type: read/write offset: dma base address + 04h default: 0000h size: two bytes
73 7.4 dma command register the dma command register enables and disables the dma controller. bit 2 (dmaen) defaults to 0 enabling the dma controller. all other bits are reserved. see table 72 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name dma command type r r r r r r/w r r default 0 0 0 0 0 0 0 0 register: dma command type: read-only, read/write offset: dma base address + 08h default: 00h size: one byte table 72. dma command register bit type type function 73 rsvd r reserved. bits 73 return 0s when read. 2 dmaen r/w dma controller enable. bit 2 enables and disables the distributed dma slave controller in the PCI1420 and defaults to the enabled state. 0 = dma controller enabled (default) 1 = dma controller disabled 10 rsvd r reserved. bits 1 and 0 return 0s when read. 7.5 dma status register the dma status register indicates the terminal count and dma request (dreq ) status. see table 73 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name dma status type r r r r r r r r default 0 0 0 0 0 0 0 0 register: dma status type: read-only offset: dma base address + 08h default: 00h size: one byte table 73. dma status register bit signal type function 74 dreqstat r channel request. in the 8237, bits 74 indicate the status of dreq of each dma channel. in the PCI1420, these bits indicate the dreq status of the single socket being serviced by this register. all four bits are set when the pc card asserts dreq and are reset when dreq is deasserted. the status of bit 0 (maskbit) in the dma multichannel/mask register (see section 7.9) has no effect on these bits. 30 tc r channel terminal count. the 8327 uses bits 30 to indicate the tc status of each of its four dma channels. in the PCI1420, these bits report information about a single dma channel; therefore, all four of these register bits indicate the tc status of the single socket being serviced by this register. all four bits are set when the tc is reached by the dma channel. these bits are reset when read or the dma channel is reset.
74 7.6 dma request register the dma request register requests a ddma transfer through software. any write to this register enables software requests, and this register is to be used in block mode only. bit 7 6 5 4 3 2 1 0 name dma request type w w w w w w w w default 0 0 0 0 0 0 0 0 register: dma request type: write-only offset: dma base address + 09h default: 00h size: one byte 7.7 dma mode register the dma mode register sets the dma transfer mode. see table 74 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name dma mode type r/w r/w r/w r/w r/w r/w r/w r default 0 0 0 0 0 0 0 0 register: dma mode type: read-only, read/write offset: dma base address + 0bh default: 00h size: one byte table 74. dma mode register bit signal type function 76 dmamode r/w mode select. the PCI1420 uses bits 7 and 6 to determine the transfer mode. 00 = demand mode select (default) 01 = single mode select 10 = block mode select 11 = reserved 5 incdec r/w address increment/decrement. the PCI1420 uses bit 5 to select the memory address in the dma current address/base address register to increment or decrement after each data transfer. this is in accordance with the 8237 use of this register bit and is encoded as follows: 0 = addresses increment (default). 1 = addresses decrement. 4 autoinit r/w auto initialization 0 = auto initialization disabled (default) 1 = auto initialization enabled 32 xfertype r/w transfer type. bits 3 and 2 select the type of direct memory transfer to be performed. a memory write transfer moves data from the PCI1420 pc card interface to memory and a memory read transfer moves data from memory to the PCI1420 pc card interface. the field is encoded as: 00 = no transfer selected (default) 01 = write transfer 10 = read transfer 11 = reserved 10 rsvd r reserved. bits 1 and 0 return 0s when read.
75 7.8 dma master clear register the dma master clear register resets the ddma controller and all ddma registers. bit 7 6 5 4 3 2 1 0 name dma master clear type w w w w w w w w default 0 0 0 0 0 0 0 0 register: dma master clear type: write-only offset: dma base address + 0dh default: 00h size: one byte 7.9 dma multichannel/mask register the PCI1420 uses only the least significant bit of this register to mask the pc card dma channel. the PCI1420 sets the mask bit when the pc card is removed. host software is responsible for either resetting the socket's dma controller or enabling the mask bit. see table 75 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name dma multichannel/mask type r r r r r r r r default 0 0 0 0 0 0 0 0 register: dma multichannel/mask type: read-only offset: dma base address + 0fh default: 00h size: one byte table 75. dma multichannel/mask register bit signal type function 71 rsvd r reserved. bits 71 return 0s when read. 0 maskbit r/w mask select. bit 0 masks incoming dreq signals from the pc card. when set, the socket ignores dma requests from the card. when cleared (or reset), incoming dreq assertions are serviced normally. 0 = ddma service provided on card dreq 1 = socket dreq signal ignored (default)
76
81 8 electrical characteristics 8.1 absolute maximum ratings over operating temperature ranges 2 supply voltage range, v cc 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clamping voltage range, v ccp, v cca, v ccb, v cci 0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i : pci 0.5 v to v ccp + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card a 0.5 to v cca + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card b 0.5 to v ccb + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . miscellaneous 0.5 to v cci + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fail safe 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o : pci 0.5 v to v ccp + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card a 0.5 to v cca + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card b 0.5 to v ccb + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . miscellaneous 0.5 to v cci + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fail safe 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 2) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . virtual junction temperature, t j 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. applies for external input and bidirectional buffers. v i > v cc does not apply to fail-safe terminals. pci terminals are measured with respect to v ccp instead of v cc . pc card terminals are measured with respect to v cca or v ccb . miscellaneous signals are measured with respect to v cci . the limit specified applies for a dc condition. 2. applies for external output and bidirectional buffers. v o > v cc does not apply to fail-safe terminals. pci terminals are measured with respect to v ccp instead of v cc . pc card terminals are measured with respect to v cca or v ccb . miscellaneous signals are measured with respect to v cci . the limit specified applies for a dc condition.
82 8.2 recommended operating conditions (see note 3) operation min nom max unit v cc core voltage commercial 3.3 v 3 3.3 3.6 v v ccp pci i/o clamp oltage commercial 3.3 v 3 3.3 3.6 v v ccp pci i/o c l amp vo l tage commercial 5 v 4.75 5 5.25 v v cca pc card i/o clamp oltage commercial 3.3 v 3 3.3 3.6 v cca v ccb pc c ar d i/o c l amp vo l tage commercial 5 v 4.75 5 5.25 v v cci miscellaneo s i/o clamp oltage commercial 3.3 v 3 3.3 3.6 v v cci mi sce ll aneous i/o c l amp vo l tage commercial 5 v 4.75 5 5.25 v 2 pci 3.3 v 0.5 v ccp v ccp 2 pci 5 v 2 v ccp 2 pc card 3.3 v 0.475 v cca/b v cca/b v ih 2 high-level input voltage pc card 5 v 2.4 v cca/b v ih miscellaneous 3 2 v cci fail safe 2 v cc cd pins 2.4 v cc 2 pci 3.3 v 0 0.3 v ccp 2 pci 5 v 0 0.8 v 2 low level input voltage pc card 3.3 v 0 0.325 v cca/b v v il 2 l ow- l eve l i npu t vo lt age pc card 5 v 0 0.8 v miscellaneous 3 0 0.8 fail safe 0 0.8 pci 0 v ccp v i in p ut voltage pc card 0 v cca/b v v i inp u t v oltage miscellaneous 3 0 v cci v fail safe 0 v cc ? pci 0 v cc v o ? out p ut voltage pc card 0 v cc v v o ? o u tp u t v oltage miscellaneous 3 0 v cc v fail safe 0 v cc pci and pc card 1 4 t t input transition time (t r and t f ) miscellaneous and fail safe 0 6 ns t a operating ambient temperature range 0 25 70 c t j # virtual junction temperature 0 25 115 c 2 applies to external inputs and bidirectional buffers without hysteresis 3 miscellaneous pins are 149, 150, 151, 152, 154, 155, 156, 157, 158, 159, 161, and 163 for the pdv packaged device and a16, b15, c14, c15, d19, e14, e17, e19, f14, f15, f17, and g15 for the ghk packaged device (suspend , spkrout, ri_out , multifunction terminals (mfunc0mfunc6), and power switch control pins). fail-safe pins are 16, 56, 68, 74, 82, 122, 134, and 140 for the pdv packaged device and h3, h17, j18, m19, p7, r9, u8, and v11 for the ghk packaged device (card detect and voltage sense pins). ? applies to external output buffers # these junction temperatures reflect simulation conditions. the customer is responsible for verifying junction temperature. cd pins are 16, 74, 82, and 140 for the pdv packaged device and h3, h17, r9, and v11 for the ghk packaged device. note 3: unused pins (input or i/o) must be held high or low to prevent them from floating.
83 8.3 electrical characteristics over recommended operating conditions (unless otherwise noted) parameter pins operation test conditions min max unit pci 3.3 v i oh = 0.5 ma 0.9 v cc pci 5 v i oh = 2 ma 2.4 v oh high-level output voltage pc card 3.3 v i oh = 0.15 ma 0.9 v cc v gg pc c ar d 5 v i oh = 0.15 ma 2.4 miscellaneous i oh =4ma v cc 06 mi sce ll aneous i oh = 4 ma v cc 0 . 6 pci 3.3 v i ol = 1.5 ma 0.1 v cc pci 5 v i ol = 6 ma 0.55 v ol low level output voltage pc card 3.3 v i ol = 0.7 ma 0.1 v cc v v ol l ow- l eve l ou t pu t vo lt age pc c ar d 5 v i ol = 0.7 ma 0.55 v miscellaneous i ol = 4 ma 0.5 serr i ol = 12 ma 0.5 i ozl 3-state, hi g h-impedance low-level out p ut p ins 3.6 v v i = v cc 1 m a i ozl ,g output current o u tp u t pins 5.25 v v i = v cc 1 m a i ozh 3-state, hi g h-impedance hi g h-level out p ut p ins 3.6 v v i = v cc 2 10 m a i ozh ,g g output current o u tp u t pins 5.25 v v i = v cc 2 25 m a i lo le el inp t c rrent input pins v i = gnd 1 m a i il l ow- l eve l i nput current i/o pins v i = gnd 10 m a in p ut p ins 3.6 v v i = v cc 3 10 inp u t pins 5.25 v v i = v cc 3 20 i ih high-level input current i/o p ins 3.6 v v i = v cc 3 10 m a i/o pins 5.25 v v i = v cc 3 25 fail-safe pins 3.6 v v i = v cc 10 2 for pci pins, v i = v ccp . for pc card pins, v i = v cc(a/b) . for miscellaneous pins, v i = v cci 3 for i/o pins, input leakage (i il and i ih ) includes i oz leakage of the disabled output. i ih is not tested in these pins: 16, 43, 45, 47, 48, 49, 50, 56, 58, 61, 68, 69, 70, 71, 72, 74, 82, 107, 108, 109, 111, 114, 115, 122, 124, 127, 134, 135, 136, 137, 138, 140, and 150 for the pdv packaged device and f17, h3, h17, h19, j14, j15, j17, j18, l14, l18, m14, m19, n5, n19, p1, p5, p6, p7, p15, p17, p19, r1, r2, r7, r9, r18, u8, v8, v9, v11, w5, w8, and w9 for the ghk packaged device because they are pu lled up with internal resistors. 8.4 pci clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature parameter alternate symbol test conditions min max unit t c cycle time, pclk t cyc 30 ns t wh pulse duration (width), pclk high t high 11 ns t wl pulse duration (width), pclk low t low 11 ns d v/ d t slew rate, pclk t r , t f 1 4 v/ns t w pulse duration (width), rstin t rst 1 ms t su setup time, pclk active at end of rstin t rst-clk 100 s
84 8.5 pci timing requirements over recommended ranges of supply voltage and operating free-air temperature this data sheet uses the following conventions to describe time ( t ) intervals. the format is t a , where subscript a indicates the type of dynamic parameter being represented. one of the following is used: t pd = propagation delay time, t d = delay time, t su = setup time, and t h = hold time. parameter alternate symbol test conditions min max unit t d pro p agation delay time see note 4 pclk-to-shared signal valid delay time t val c l = 50 pf, 11 ns t pd propagation dela y time , see note 4 pclk-to-shared signal invalid delay time t inv l , see note 4 2 ns t en enable time, high impedance-to-active delay time from pclk t on 2 ns t dis disable time, active-to-high impedance delay time from pclk t off 28 ns t su setup time before pclk valid t su 7 ns t h hold time after pclk high t h 0 ns note 4: pci shared signals are ad31ad0, c/be3 c/be0 , frame , trdy , irdy , stop , idsel, devsel , and par.
91 9 mechanical information the PCI1420 is packaged in either a 209-ball ghk bga or a 208-pin pdv package. the following shows the mechanical dimensions for the ghk and pdv packages. ghk (s-pbga-n209) plastic ball grid array 19 14,40 typ 17 16 13 14 15 11 12 9 810 v u w r n p l m k t 7 5 6 3 4 h f g e c d 1 a b 2 j 18 seating plane 41452732/b 12/98 sq 16,10 15,90 0,95 0,45 0,35 0,55 0,45 0,12 0,08 0,85 1,40 max 0,10 0,80 0,80 m 0,08 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. micro star ? bga configuration. micro star is a trademark of texas instruments incorporated.
92 pdv (s-pqfp-g208) plastic quad flatpack 0,13 nom 105 104 53 0,27 0,17 0,25 0,45 0,75 0,05 min 52 seating plane 4087729/b 06/96 157 208 156 sq sq 28,05 29,90 30,10 27,95 25,50 typ 1 1,60 max 0,08 0,50 m 0,08 0 7 gage plane 1,35 1,45 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec mo-136
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated

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